Formal hardware verification: methods and systems in comparison
Gespeichert in:
| Format: | Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
Springer
1997
|
| Schriftenreihe: | Lecture notes in computer science
1287 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XII, 367 S. graph. Darst. |
| ISBN: | 3540634754 |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV011497762 | ||
| 003 | DE-604 | ||
| 005 | 20030512 | ||
| 007 | t| | ||
| 008 | 970805s1997 gw d||| |||| 00||| eng d | ||
| 016 | 7 | |a 950994286 |2 DE-101 | |
| 020 | |a 3540634754 |9 3-540-63475-4 | ||
| 035 | |a (OCoLC)37437677 | ||
| 035 | |a (DE-599)BVBBV011497762 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 044 | |a gw |c DE | ||
| 049 | |a DE-91G |a DE-384 |a DE-739 |a DE-20 |a DE-19 |a DE-29T |a DE-706 |a DE-521 |a DE-634 |a DE-83 |a DE-188 | ||
| 050 | 0 | |a TK7874.75.F67 1997 | |
| 082 | 0 | |a 621.39/5 |2 21 | |
| 082 | 0 | |a 621.39/5 21 | |
| 084 | |a DAT 190f |2 stub | ||
| 084 | |a 28 |2 sdnb | ||
| 245 | 1 | 0 | |a Formal hardware verification |b methods and systems in comparison |c Thomas Kropf (ed.) |
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 1997 | |
| 300 | |a XII, 367 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Lecture notes in computer science |v 1287 | |
| 650 | 7 | |a C@S |2 inriac | |
| 650 | 7 | |a COSPAN |2 inriac | |
| 650 | 7 | |a Circuits intégrés à très grande échelle - Conception et construction |2 ram | |
| 650 | 7 | |a Conception assistée par ordinateur |2 ram | |
| 650 | 7 | |a Hardware |2 gtt | |
| 650 | 7 | |a MDG |2 inriac | |
| 650 | 7 | |a PVS |2 inriac | |
| 650 | 7 | |a STE |2 inriac | |
| 650 | 7 | |a VHDL |2 inriac | |
| 650 | 7 | |a vérification matériel |2 inriac | |
| 650 | 4 | |a Integrated circuits -- Very large scale integration -- Computer-aided design | |
| 650 | 4 | |a Integrated circuits -- Verification | |
| 650 | 4 | |a Formal methods (Computer science) | |
| 650 | 0 | 7 | |a Hardwareverifikation |0 (DE-588)4214982-4 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Hardwareverifikation |0 (DE-588)4214982-4 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Kropf, Thomas |e Sonstige |4 oth | |
| 830 | 0 | |a Lecture notes in computer science |v 1287 |w (DE-604)BV000000607 |9 1287 | |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007737752&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007737752 | |
Datensatz im Suchindex
| _version_ | 1820874854373523456 |
|---|---|
| adam_text |
TABLE
OF
CONTENTS
PREFACE
.
V
LIST
OF
CONTRIBUTORS
.
1
SYMBOLIC
TRAJECTORY
EVALUATION
SCOTT
HAZELHURST
AND
CARL-JOHAN
H.
SEGER
.
3
1.
INTRODUCTION
.
3
1.1
OVERVIEW
OF
STE
AND
VERIFICATION
METHOD
.
3
1.2
HISTORY
OF
SYMBOLIC
TRAJECTORY
EVALUATION
.
5
1.3
OUTLINE
OF
CHAPTER
.
6
2.
RELATED
WORK
.
7
2.1
MODEL
CHECKING
ALGORITHMS
.
7
2.2
ABSTRACTION
.
8
2.3
COMPOSITIONAL
REASONING
.
9
3.
BASICS
.
10
3.1
THE
MODEL
STRUCTURE
.
11
3.2
THE
QUATERNARY
LOGIC
Q
.
12
3.3
THE
TEMPORAL
LOGIC
.
14
4.
MODELLING
HARDWARE
.
21
4.1
MODELLING
ISSUES
.
21
4.2
CIRCUIT
MODELS
AS
STATE
SPACES
.
22
5.
SPECIFICATION
AND
PROOF
TECHNIQUES
.
24
5.1
VERIFICATION
ASSERTIONS
.
24
5.2
TRAJECTORY
EVALUATION
.
25
5.3
COMPOSITIONAL
THEORY
.
32
5.4
THE
VOSS
VERIFICATION
SYSTEM:
THE
FRONT
END
.
39
5.5
VERIFICATION
STYLE
.
40
6.
EXPERIMENTAL
WORK
.
;
.
41
6.1
BENCHMARK
11:
BLACKJACK
DEALER
.
42
6.2
BENCHMARK
17:
MULTIPLIER
.
44
6.3
IEEE
FP
MULTIPLIER
.
49
6.4
BENCHMARK
21:
ONE
DIMENSIONAL
SYSTOLIC
ARRAY
.
49
6.5
BENCHMARK
22:
TWO
DIMENSIONAL
SYSTOLIC
ARRAY
.
54
VIII
TABLE
OF
CONTENTS
6.6
BENCHMARK
20:
ASSOCIATIVE
MEMORY
.
58
6.7
LIVENESS
PROPERTIES:
BENCHMARKS
7
AND
12
.
62
7.
CONCLUSION
.
65
7.1
SUMMARY
.
65
7.2
LIMITATIONS
OF
SPECIFICATION
.
65
7.3
TOOL-BUILDING
EXPERIENCE
.
66
7.4
FUTURE
WORK
.
68
A.
APPENDIX
.
69
A.L
BENCHMARK
17
.
69
A.2
FL
CODE
FOR
PROOF
OF
MULTIPLIER
.
76
VERIFICATION
WITH
ABSTRACT
STATE
MACHINES
USING
MDGS
E.
CERNY,
F.
CORELLA,
M.
LANGEVIN,
X.
SONG,
S.
TAHAR,
AND
Z.
ZHOU
.
79
1.
INTRODUCTION
.
79
1.1
MOTIVATIONS
.
79
1.2
LIMITATIONS
OF
THE
APPROACH
.
80
1.3
RELATED
WORK
.
81
1.4
OUTLINE
.
83
2.
FOUNDATIONS
OF
THE
METHODOLOGY
.
84
2.1
LOGIC
.
84
2.2
MULTIWAY
DECISION
GRAPHS
.
87
2.3
ABSTRACT
STATE
MACHINES
.
93
3.
MODELING
HARDWARE
WITH
MDGS
.
96
4.
MDG-BASED
VERIFICATION
TECHNIQUES
.
99
4.1
COMBINATIONAL
CIRCUITS
.
99
4.2
SEQUENTIAL
CIRCUITS
.
100
5.
VERIFICATION
OF
BENCHMARK
CIRCUITS
.
103
6.
FAIRISLE
ATM
SWITCH
FABRIC:
A
CASE
STUDY
IN
VERIFICATION
USING
MDGS
104
6.1
THE
FAIRISLE
ATM
SWITCH
FABRIC
.
105
6.2
MDG
MODELS
.
107
6.3
VERIFICATION
.
109
7.
CONCLUSIONS
AND
FUTURE
WORK
.
112
DESIGN
VERIFICATION
USING
SYNCHRONIZED
TRANSITIONS
JPRGEN
STAUNSTRUP
.
114
1.
INTRODUCTION
.
114
2.
RELATED
WORK
.
115
3.
BASICS
.
116
3.1
NOTATION
.
116
3.2
DESIGN
OF
A
BLACK-JACK
DEALER
.
122
3.3
TRANSLATION
.
124
4.
MODELING
HARDWARE
.
124
4.1
DIRECT
REALIZATIONS
.
125
4.2
CLOCKED
REALIZATIONS
.
127
TABLE
OF
CONTENTS
IX
4.3
MODELING
EXISTING
CIRCUITS
.
128
4.4
EVALUATION
.
129
5.
VERIFICATION
TECHNIQUE
.
130
5.1
INDUCTIVE
VERIFICATION
.
131
5.2
MECHANIZATION
.
132
5.3
MODULAR
DESIGNS
.
133
5.4
EVALUATION
.
135
5.5
LIVENESS
PROPERTIES
.
136
6.
REFINEMENT
.
137
6.1
DESIGN
OF
THE
SINGLE-PULSER
.
138
6.2
FORMAL
VERIFICATION
OF
REFINEMENT
.
140
6.3
EVALUATION
.
142
7.
SYNCHRONOUS
DESIGNS
.
142
7.1
THE
ISYST
.
142
7.2
THE
SYNCHRONOUS
COMBINATOR
.
143
7.3
QUANTIFICATION
.
145
8.
EXPERIMENTAL
RESULTS
.
146
8.1
VERIFYING
THE
BLACK-JACK
DESIGN
.
146
8.2
SINGLE
PULSER
.
147
8.3
ISYST
.
148
8.4
FIFO
QUEUE
.
148
8.5
ARBITER
.
151
8.6
EVALUATION
.
153
9.
CONCLUSION
.
154
HARDWARE
VERIFICATION
USING
PVS
MANDAYAM
SRIVAS,
HARALD
RUEFI,
AND
DAVID
CYRLUK
.
156
1.
INTRODUCTION
.
156
2.
RELATED
WORK
.
157
3.
BASICS
.
158
3.1
THE
SPECIFICATION
LANGUAGE
.
158
3.2
THE
PROOF
CHECKER
.
160
3.3
GROUND
DECISION
PROCEDURES
AND
REWRITING
.
160
3.4
THE
POWER
OF
INTERACTION
.
162
3.5
INTEGRATION
OF
MODEL
CHECKING
INTO
PVS
.
162
3.6
HIGH-LEVEL
STRATEGIES
.
164
4.
MODELING
HARDWARE
.
164
4.1
PREDICATIVE
STYLE
SPECIFICATIONS
.
165
4.2
FUNCTIONAL
STYLE
SPECIFICATIONS
.
168
4.3
FUNCTIONAL
DESCRIPTION
OF
COMBINATIONAL
CIRCUITS
.
171
4.4
GENERIC
HARDWARE
COMPONENTS
.
173
5.
MICROPROCESSOR
VERIFICATION
.
174
5.1
A
HISTORICAL
PERSPECTIVE
OF
MICROPROCESSOR
VERIFICATION
.
174
5.2
GENERAL
MICROPROCESSOR
CORRECTNESS
.
175
X
TABLE
OF
CONTENTS
5.3
A
GENERAL
PVS
FRAMEWORK
FOR
VERIFYING
MICROPROCESSORS
.
176
5.4
FORMALIZING
THE
CORRECTNESS
CONDITION
.
177
5.5
VERIFYING
THE
TAMARACK
PROCESSOR
.
179
5.6
VERIFYING
PIPELINED
MICROPROCESSORS
.
183
5.7
MECHANIZATION
OF
PROOFS
OF
VERIFICATION
CONDITIONS
.
189
5.8
VERIFICATION
OF
INDUSTRIAL-STRENGTH
MICROPROCESSORS
.
190
6.
VERIFICATION
OF
ARITHMETIC
CIRCUITS
.
192
6.1
VERIFICATION
OF
ITERATIVE
ARRAY
MULTIPLIERS
.
193
6.2
VERIFICATION
OF
SRT
DIVISION
.
197
7.
EXPERIMENTAL
RESULTS
.
200
7.1
VERIFYING
THE
SINGLE
PULSER
.
200
7.2
VERIFYING
THE
ARBITER
.
201
7.3
VERIFYING
THE
BLACK-JACK
DESIGN
.
204
7.4
VERIFYING
THE
FIR
FILTER
.
204
8.
CONCLUSIONS
.
205
VERIFYING
VHDL
DESIGNS
WITH
COSPAN
KATHI
FISLER
AND
ROBERT
P.
KURSHAN
.
206
1.
INTRODUCTION
.
206
2.
RELATED
WORK
.
209
3.
THE
PROGRAM
SEMANTICS
.
210
4.
THE
SEMANTICS
OF
VERIFICATION
.
214
5.
OPERATIONAL
VERIFICATION
.
219
6.
EXPERIMENTAL
RESULTS
.
222
6.1
SINGLE
PULSER
.
223
6.2
ARBITER
.
228
6.3
SYSTOLIC
ARRAY
ELEMENT
.
230
6.4
BLACKJACK
DEALER
.
234
6.5
CAR
SEAT
CONTROLLER
.
235
7.
SUMMARY
.
244
A.
APPENDIX:
AUTOMATA
DEFINITIONS
.
244
A.L
ASSUMEALWAYS_()
.
245
A.2
NEVER_()
.
245
A.3
AFTER_EVENTUALLY_()
.
246
A.4
PHASE
.
246
A.5
AFTER_NEVER-UNLESS_()
.
247
A.6
AFTER_EVENTUALLY_UNLESS_()
.
247
THE
CQS
SYSTEM
KLAUS
SCHNEIDER
AND
THOMAS
KROPF
.
248
1.
INTRODUCTION
.
248
2.
RELATED
WORK
.
252
2.1
HARDWARE
VERIFICATION
USING
TEMPORAL
LOGICS
.
252
2.2
HARDWARE
VERIFICATION
BASED
ON
PREDICATE
LOGICS
.
254
TABLE
OF
CONTENTS
XI
2.3
COMBINED
APPROACHES
.
;
.
255
2.4
OUTLINE
OF
THE
CHAPTER
.
256
3.
BASICS
.
257
3.1
UNDERLYING
FORMALISM
OF
COS
.
257
3.2
FAIR
PREFIX
AUTOMATA
.
261
3.3
REWRITE-BASED
THEOREM
PROVING
FOR
ABSTRACT
DATA
TYPES
.
262
4.
MODELLING
HARDWARE
.
265
4.1
DESCRIBING
NONGENERIC
STRUCTURES
.
266
4.2
DESCRIBING
REGULAR
STRUCTURES
.
268
5.
SPECIFICATION
AND
PROOF
.
273
5.1
THE
UNIFYING
PRINCIPLE
.
273
5.2
STRATEGIES
FOR
VERIFYING
TEMPORAL
BEHAVIOR
.
274
5.3
TRANSLATING
LTL
FORMULAS
INTO
FAIR
PREFIX
FORMULAE
.
275
5.4
STRATEGIES
FOR
VERIFYING
ABSTRACT
DATA
TYPES
.
282
5.5
COMBINING
THE
STRATEGIES
.
284
6.
EXPERIMENTAL
RESULTS
.
285
6.1
SINGLE
PULSER
.
286
6.2
BLACK
JACK
DEALER
.
287
6.3
SAFE
BOX
.
291
6.4
THE
ISLAND
TUNNEL
CONTROLLER
.
297
6.5
ARBITER
.
303
6.6
VON
NEUMANN
ADDER
.
307
6.7
SEQUENTIAL
MULTIPLIER
CIRCUITS
.
310
6.8
SYSTOLIC
ARRAYS
.
312
6.9
GSM
SPEECH
ENCODING
.
317
7.
CONCLUSIONS
.
328
APPENDIX:
THE
COMMON
BOOK
EXAMPLES
THOMAS
KROPF
.
330
1.
INTRODUCTION
.
330
2.
SINGLE
PULSER
.
330
2.1
INTRODUCTION
.
331
2.2
SPECIFICATION
.
331
2.3
IMPLEMENTATION
.
331
2.4
ACKNOWLEDGEMENTS
.
332
3.
ARBITER
.
332
3.1
INTRODUCTION
.
332
3.2
SPECIFICATION
.
332
3.3
IMPLEMENTATION
.
333
3.4
ACKNOWLEDGMENTS
.
334
4.
BLACK-JACK
DEALER
.
334
4.1
SPECIFICATION
.
334
4.2
IMPLEMENTATION
.
334
4.3
ACKNOWLEDGMENTS
.
337
XII
TABLE
OF
CONTENTS
5.
LSYST
(FILTER)
.
.,
.
337
5.1
INTRODUCTION
.
337
5.2
SPECIFICATION
.
340
5.3
IMPLEMENTATION
.
341
5.4
ACKNOWLEDGEMENTS
.
343
REFERENCES
.
349 |
| any_adam_object | 1 |
| building | Verbundindex |
| bvnumber | BV011497762 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874.75.F67 1997 |
| callnumber-search | TK7874.75.F67 1997 |
| callnumber-sort | TK 47874.75 F67 41997 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | SS 4800 |
| classification_tum | DAT 190f |
| ctrlnum | (OCoLC)37437677 (DE-599)BVBBV011497762 |
| dewey-full | 621.39/5 621.39/521 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 621.39/5 21 |
| dewey-search | 621.39/5 621.39/5 21 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000 cb4500</leader><controlfield tag="001">BV011497762</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20030512</controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">970805s1997 gw d||| |||| 00||| eng d</controlfield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">950994286</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">3540634754</subfield><subfield code="9">3-540-63475-4</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)37437677</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV011497762</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">gw</subfield><subfield code="c">DE</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield><subfield code="a">DE-384</subfield><subfield code="a">DE-739</subfield><subfield code="a">DE-20</subfield><subfield code="a">DE-19</subfield><subfield code="a">DE-29T</subfield><subfield code="a">DE-706</subfield><subfield code="a">DE-521</subfield><subfield code="a">DE-634</subfield><subfield code="a">DE-83</subfield><subfield code="a">DE-188</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7874.75.F67 1997</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield><subfield code="2">21</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5 21</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 190f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">28</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Formal hardware verification</subfield><subfield code="b">methods and systems in comparison</subfield><subfield code="c">Thomas Kropf (ed.)</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Berlin [u.a.]</subfield><subfield code="b">Springer</subfield><subfield code="c">1997</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XII, 367 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Lecture notes in computer science</subfield><subfield code="v">1287</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">C@S</subfield><subfield code="2">inriac</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">COSPAN</subfield><subfield code="2">inriac</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Circuits intégrés à très grande échelle - Conception et construction</subfield><subfield code="2">ram</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Conception assistée par ordinateur</subfield><subfield code="2">ram</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Hardware</subfield><subfield code="2">gtt</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">MDG</subfield><subfield code="2">inriac</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">PVS</subfield><subfield code="2">inriac</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">STE</subfield><subfield code="2">inriac</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">VHDL</subfield><subfield code="2">inriac</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">vérification matériel</subfield><subfield code="2">inriac</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits -- Very large scale integration -- Computer-aided design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits -- Verification</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Formal methods (Computer science)</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Hardwareverifikation</subfield><subfield code="0">(DE-588)4214982-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Hardwareverifikation</subfield><subfield code="0">(DE-588)4214982-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kropf, Thomas</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Lecture notes in computer science</subfield><subfield code="v">1287</subfield><subfield code="w">(DE-604)BV000000607</subfield><subfield code="9">1287</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">DNB Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007737752&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-007737752</subfield></datafield></record></collection> |
| id | DE-604.BV011497762 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T15:06:21Z |
| institution | BVB |
| isbn | 3540634754 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007737752 |
| oclc_num | 37437677 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-384 DE-739 DE-20 DE-19 DE-BY-UBM DE-29T DE-706 DE-521 DE-634 DE-83 DE-188 |
| owner_facet | DE-91G DE-BY-TUM DE-384 DE-739 DE-20 DE-19 DE-BY-UBM DE-29T DE-706 DE-521 DE-634 DE-83 DE-188 |
| physical | XII, 367 S. graph. Darst. |
| publishDate | 1997 |
| publishDateSearch | 1997 |
| publishDateSort | 1997 |
| publisher | Springer |
| record_format | marc |
| series | Lecture notes in computer science |
| series2 | Lecture notes in computer science |
| spelling | Formal hardware verification methods and systems in comparison Thomas Kropf (ed.) Berlin [u.a.] Springer 1997 XII, 367 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 1287 C@S inriac COSPAN inriac Circuits intégrés à très grande échelle - Conception et construction ram Conception assistée par ordinateur ram Hardware gtt MDG inriac PVS inriac STE inriac VHDL inriac vérification matériel inriac Integrated circuits -- Very large scale integration -- Computer-aided design Integrated circuits -- Verification Formal methods (Computer science) Hardwareverifikation (DE-588)4214982-4 gnd rswk-swf Hardwareverifikation (DE-588)4214982-4 s DE-604 Kropf, Thomas Sonstige oth Lecture notes in computer science 1287 (DE-604)BV000000607 1287 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007737752&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Formal hardware verification methods and systems in comparison Lecture notes in computer science C@S inriac COSPAN inriac Circuits intégrés à très grande échelle - Conception et construction ram Conception assistée par ordinateur ram Hardware gtt MDG inriac PVS inriac STE inriac VHDL inriac vérification matériel inriac Integrated circuits -- Very large scale integration -- Computer-aided design Integrated circuits -- Verification Formal methods (Computer science) Hardwareverifikation (DE-588)4214982-4 gnd |
| subject_GND | (DE-588)4214982-4 |
| title | Formal hardware verification methods and systems in comparison |
| title_auth | Formal hardware verification methods and systems in comparison |
| title_exact_search | Formal hardware verification methods and systems in comparison |
| title_full | Formal hardware verification methods and systems in comparison Thomas Kropf (ed.) |
| title_fullStr | Formal hardware verification methods and systems in comparison Thomas Kropf (ed.) |
| title_full_unstemmed | Formal hardware verification methods and systems in comparison Thomas Kropf (ed.) |
| title_short | Formal hardware verification |
| title_sort | formal hardware verification methods and systems in comparison |
| title_sub | methods and systems in comparison |
| topic | C@S inriac COSPAN inriac Circuits intégrés à très grande échelle - Conception et construction ram Conception assistée par ordinateur ram Hardware gtt MDG inriac PVS inriac STE inriac VHDL inriac vérification matériel inriac Integrated circuits -- Very large scale integration -- Computer-aided design Integrated circuits -- Verification Formal methods (Computer science) Hardwareverifikation (DE-588)4214982-4 gnd |
| topic_facet | C@S COSPAN Circuits intégrés à très grande échelle - Conception et construction Conception assistée par ordinateur Hardware MDG PVS STE VHDL vérification matériel Integrated circuits -- Very large scale integration -- Computer-aided design Integrated circuits -- Verification Formal methods (Computer science) Hardwareverifikation |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007737752&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000000607 |
| work_keys_str_mv | AT kropfthomas formalhardwareverificationmethodsandsystemsincomparison |