Field programmable logic and applications: 7th international workshop, FPL '97, London, UK, September 1 - 3, 1997 ; proceedings
Gespeichert in:
| Format: | Tagungsbericht Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
Springer
1997
|
| Schriftenreihe: | Lecture notes in computer science
1304 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XI, 503 S. Ill., graph. Darst. |
| ISBN: | 3540634657 |
Internformat
MARC
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| 245 | 1 | 0 | |a Field programmable logic and applications |b 7th international workshop, FPL '97, London, UK, September 1 - 3, 1997 ; proceedings |c Wayne Luk ... (eds.) |
| 246 | 1 | 3 | |a Field-programmable logic and applications |
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 1997 | |
| 300 | |a XI, 503 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Lecture notes in computer science |v 1304 | |
| 650 | 7 | |a FPGA |2 inriac | |
| 650 | 7 | |a Hardware |2 gtt | |
| 650 | 7 | |a Réseaux logiques programmables - Congrès |2 ram | |
| 650 | 7 | |a reconfiguration |2 inriac | |
| 650 | 7 | |a robotique |2 inriac | |
| 650 | 7 | |a réseau logique programmable |2 inriac | |
| 650 | 7 | |a traitement image |2 inriac | |
| 650 | 7 | |a traitement signal |2 inriac | |
| 650 | 7 | |a vidéo |2 inriac | |
| 650 | 4 | |a Field programmable gate arrays -- Congresses | |
| 650 | 4 | |a Programmable array logic -- Congresses | |
| 650 | 0 | 7 | |a Gate-Array-Bauelement |0 (DE-588)4113666-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Programmierbare logische Anordnung |0 (DE-588)4076369-9 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 1997 |z London |2 gnd-content | |
| 689 | 0 | 0 | |a Programmierbare logische Anordnung |0 (DE-588)4076369-9 |D s |
| 689 | 0 | 1 | |a Gate-Array-Bauelement |0 (DE-588)4113666-4 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Luk, Wayne |e Sonstige |4 oth | |
| 711 | 2 | |a FPL |n 7 |d 1997 |c London |j Sonstige |0 (DE-588)2165008-1 |4 oth | |
| 830 | 0 | |a Lecture notes in computer science |v 1304 |w (DE-604)BV000000607 |9 1304 | |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007737703&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007737703 | |
Datensatz im Suchindex
| _version_ | 1820874854360940544 |
|---|---|
| adam_text |
TABLE
OF
CONTENTS
DEVICES
AND
ARCHITECTURES
MULTICONTEXT
DYNAMIC
RECONFIGURATION
AND
REAL
TIME
PROBING
ON
A
NOVEL
MIXED
SIGNAL
PROGRAMMABLE
DEVICE
WITH
ON-CHIP
MICROPROCESSOR
.
1
J.
FAURA,
J.M.
MORENO,
M.A.
AGUIRRE,
P.
VAN
DUONG
AND
J.M.
INSENSER
CAD-ORIENTED
FPGA
AND
DEDICATED
CAD
SYSTEM
FOR
TELECOMMUNICATIONS
.
11
T.
MIYAZAKI,
A.
TAKAHARA,
M.
KATAYAMA,
T.
MUROOKA,
T.
ICHIMORI,
K.
FUKAMI,
A.
TSUTSUI
AND
K.
HAYASHI
ROTHKO:
A
THREE
DIMENSIONAL
FPGA
ARCHITECTURE,
ITS
FABRICATION,
AND
DESIGN
TOOLS
.
21
M.
LEESER,
W.M.
MELEIS,
M.M.
VAI
AND
P.
ZAVRACKY
EXTENDING
DYNAMIC
CIRCUIT
SWITCHING
TO
MEET
THE
CHALLENGES
OF
NEW
FPGA
ARCHITECTURES
.
31
G.
MCGREGOR
AND
P.
LYSAGHT
PERFORMANCE
EVALUATION
OF
A
FULL
SPEED
PCI
INITIATOR
AND
TARGET
SUBSYSTEM
USING
FPGAS
.
41
D.
ROBINSON,
P.
LYSAGHT,
G.
MCGREGOR
AND
H.
DICK
IMPLEMENTATION
OF
PIPELINED
MULTIPLIERS
ON
XILINX
FPGAS
.
51
T.-T.
DO,
H.
KROPP,
M.
SCHWIEGERSHAUSEN
AND
P.
PIRSCH
THE
XC6200DS
DEVELOPMENT
SYSTEM
.
61
S.
NISBET
AND
S.A.
GUCCIONE
DEVICES
AND
SYSTEMS
THERMAL
MONITORING
ON
FPGAS
USING
RING-OSCILLATORS
.
69
E.
BOEMO
AND
S.
LOPEZ-BUEDO
A
RECONFIGURABLE
APPROACH
TO
LOW
COST
MEDIA
PROCESSING
.
79
I.
KOSTARNOV,
S.
MORLEY,
J.
OSMANY
AND
C.
SOLOMON
RILEY-2:
A
FLEXIBLE
PLATFORM
FOR
CODESIGN
AND
DYNAMIC
RECONFIGURABLE
COMPUTING
RESEARCH
.
91
P.I.
MACKINLAY,
P.
Y.K.
CHEUNG,
W.
LUK
AND
R.
SANDIFORD
VIII
RECONFIGURATION
I
STREAM
SYNTHESIS
FOR
A
WORMHOLE
RUN-TIME
RECONFIGURABLE
PLATFORM
.
101
B.
KAHNE
AND
P.
ATHANAS
PIPELINE
MORPHING
AND
VIRTUAL
PIPELINES
.
ILL
W.
LUK,
N.
SHIRAZI,
S.R.
GUO
AND
P.
Y.K.
CHEUNG
PARALLEL
GRAPH
COLOURING
USING
FPGAS
.
121
B.
RISING,
M.
VAN
DAALEN,
P.
BURGE
AND
J.
SHAWE-TAYLOR
RUN-TIME
COMPACTION
OF
FPGA
DESIGNS
.
131
0.
DIESSEL
AND
H.
ELGINDY
PARTIAL
RECONFIGURATION
OF
FPGA
MAPPED
DESIGNS
WITH
APPLICATIONS
TO
FAULT
TOLERANCE
AND
YIELD
ENHANCEMENT
.
141
J.M.
EMMERT
AND
D.
BHATIA
A
CASE
STUDY
OF
PARTIALLY
EVALUATED
HARDWARE
CIRCUITS:
KEY-SPECIFIC
DES
.
151
J.
LEONARD
AND
W.H.
MANGIONE-SMITH
RUN-TIME
PARAMETERISED
CIRCUITS
FOR
THE
XILINX
XC6200
R.
PAYNE
.
161
RECONFIGURATION
II
AUTOMATIC
IDENTIFICATION
OF
SWAPPABLE
LOGIC
UNITS
IN
XC6200
CIRCUITRY
.
173
G.
BREBNER
TOWARDS
AN
EXPERT
SYSTEM
FOR
A
PRIORI
ESTIMATION
OF
RECONFIGURATION
LATENCY
IN
DYNAMICALLY
RECONFIGURABLE
LOGIC
.
183
P.
LYSAGHT
EXPLOITING
RECONFIGURABILITY
THROUGH
DOMAIN-SPECIFIC
SYSTEMS
.
193
B.L.
HUTCHINGS
DESIGN
TOOLS
TECHNOLOGY
MAPPING
BY
BINATE
COVERING
.
203
M.Z.
SERRNT
AND
K.
YI
VPR:
A
NEW
PACKING,
PLACEMENT
AND
ROUTING
TOOL
FOR
FPGA
RESEARCH
.
213
V.
BETZ
AND
J.
ROSE
IX
TECHNOLOGY
MAPPING
OF
HETEROGENEOUS
LUT-BASED
FPGAS
.
223
M.K.
INUANI
AND
J.
SAUL
TECHNOLOGY-DRIVEN
FSM
PARTITIONING
FOR
SYNTHESIS
OF
LARGE
SEQUENTIAL
CIRCUITS
TARGETING
LOOKUP-TABLE
BASED
FPGAS
.
235
K.
FESKE,
S.
MULKA,
M.
KOEGST
AND
G.
ELST
TECHNOLOGY
MAPPING
OF
LUT
BASED
FPGAS
FOR
DELAY
OPTIMISATION
.
245
X.
LIN,
E.
DAGLESS
AND
A.
LU
AUTOMATIC
MAPPING
OF
ALGORITHMS
ONTO
MULTIPLE
FPGA-SRAM
MODULES
.
255
S.J.B.
ACOCK
AND
K.R.
DIMOND
FPLD
HDL
SYNTHESIS
EMPLOYING
HIGH-LEVEL
EVOLUTIONARY
ALGORITHM
OPTIMISATION
.
265
R.B.
MAUNDER,
Z.A.
SALCIC
AND
G.G.
COGHILL
A
HARDWARE/SOFTWARE
PARTITIONING
ALGORITHM
FOR
CUSTOM
COMPUTING
MACHINES
.
274
A.V.
CHICHKOV
AND
C.B.
ALMEIDA
CUSTOM
COMPUTING
AND
CODESIGN
THE
JAVA
ENVIRONMENT
FOR
RECONFIGURABLE
COMPUTING
.
284
E.
LECHNER
AND
S.A.
GUCCIONE
DATA
SCHEDULING
TO
INCREASE
PERFORMANCE
OF
PARALLEL
ACCELERATORS
.
294
R.
W.
HARTENSTEIN,
J.
BECKER,
M.
HERZ
AND
U.
NAGELDINGER
AN
OPERATING
SYSTEM
FOR
CUSTOM
COMPUTING
MACHINES
BASED
ON
THE
XPUTER
PARADIGM
.
304
R.
KRESS,
R.W.
HARTENSTEIN
AND
U.
NAGELDINGER
SIGNAL
PROCESSING
FAST
PARALLEL
IMPLEMENTATION
OF
DFT
USING
CONFIGURABLE
DEVICES
.
314
A.
DANDALIS
AND
V.K.
PRASANNA
ENHANCING
FIXED
POINT
DSP
PROCESSOR
PERFORMANCE
BY
ADDING
CPLDS
AS
COPROCESSING
ELEMENTS
.
324
D.
GREENFIELD,
C.
CROME,
M.S.
WON
AND
D.
AMOS
A
CASE
STUDY
OF
ALGORITHM
IMPLEMENTATION
IN
RECONFIGURABLE
HARDWARE
AND
SOFTWARE
.
333
M.
SHAND
X
A
RECONFIGURABLE
DATA-LOCALISED
ARRAY
FOR
MORPHOLOGICAL
ALGORITHMS
.
344
A.S.
CHAUDHURI,
P.Y.K.
CHEUNG
AND
W.
LUK
VIRTUAL
RADIX
ARRAY
PROCESSORS
(V-RAAP)
.
354
B.
BRAMER,
D.
CHAUHAM,
M.K.
IBRAHIM
AND
A.
AGGOUN
AN
FPGA
IMPLEMENTATION
OF
A
MATCHED
FILTER
DETECTOR
FOR
SPREAD
SPECTRUM
COMMUNICATIONS
SYSTEMS
.
364
T.
MATHEWS,
S.G.
GIBB,
L.E.
TURNER,
P.J.W.
GRAUMANN
AND
M.
FATTOUCHE
AN
NTSC
AND
PAL
CLOSED
CAPTION
PROCESSOR
.
374
S.
TEERAPANYAWATT
AND
K.
ATHIKULWONGSE
IMAGE
AND
VIDEO
PROCESSING
A
800
MPIXEL/SEC
RECONFIGURABLE
IMAGE
CORRELATOR
ON
XC6216
.
382
T.
KEAN
AND
A.
DUNCAN
A
RECONFIGURABLE
COPROCESSOR
FOR
A
PCI-BASED
REAL
TIME
COMPUTER
VISION
SYSTEM
.
392
F.
LISA,
F.
CUADRADO,
D.
REXACHS
AND
J.
CARRABINA
REAL-TIME
STEREOPSIS
USING
FPGAS
.
400
P.
DUNN
AND
P.
CORKE
SENSORS,
GRAPHICS
AND
OTHER
APPLICATIONS
FPGA
IMPLEMENTATION
OF
A
DIGITAL
IQ
DEMODULATOR
USING
VHDL
.
410
C.C.
JONG,
Y.Y.H.
LAM
AND
L.S.
NG
HARDWARE
COMPILATION,
CONFIGURABLE
PLATFORMS
AND
ASICS
FOR
SELF-VALIDATING
SENSORS
.
418
I.
PAGE
POSTSCRIPTYY
RENDERING
WITH
VIRTUAL
HARDWARE
.
428
S.
SINGH,
J.
PATTERSON,
J.
BUMS
AND
M.
DALES
P4:
A
PLATFORM
FOR
FPGA
IMPLEMENTATION
OF
PROTOCOL
BOOSTERS
.
438
I.
HADZIC
AND
J.M.
SMITH
SATISFIABILITY
ON
RECONFIGURABLE
HARDWARE
.
448
M.
ABRAMOVICI
AND
D.
SAAB
AUTO-CONFIGURABLE
ARRAY
FOR
GCD
COMPUTATION
.
457
T.
JEBELEAN
XI
STRUCTURAL
VERSUS
ALGORITHMIC
APPROACHES
FOR
EFFICIENT
ADDERS
ON
XILINX
5200
FPGA
.
462
B.
LAURENT,
G.
BOSCO
AND
G.
SAUCIER
CONTROL
AND
ROBOTICS
FPGA
IMPLEMENTATION
OF
REAL-TIME
DIGITAL
CONTROLLERS
USING
ON-LINE
ARITHMETIC
.
472
A.
TISSERAND
AND
M.
DIMMLER
A
PROTOTYPING
ENVIRONMENT
FOR
FUZZY
CONTROLLERS
.
482
T.
HOLLSTEIN,
A.
KIRSCHBAUM
AND
M.
GLESNER
A
RECONFIGURABLE
SENSOR-DATA
PROCESSING
SYSTEM
FOR
PERSONAL
ROBOTS
.
.491
K.
NUKATA,
Y.
SHIBATA,
H.
AMANO
AND
Y.
ANZAI
AUTHOR
INDEX
.
501 |
| any_adam_object | 1 |
| building | Verbundindex |
| bvnumber | BV011497708 |
| callnumber-first | T - Technology |
| callnumber-label | TK7895 |
| callnumber-raw | TK7895.G36F55 1997 |
| callnumber-search | TK7895.G36F55 1997 |
| callnumber-sort | TK 47895 G36 F55 41997 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | SS 1997 SS 4800 |
| classification_tum | ELT 360f |
| ctrlnum | (OCoLC)37437546 (DE-599)BVBBV011497708 |
| dewey-full | 621.39/5 621.39/521 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 621.39/5 21 |
| dewey-search | 621.39/5 621.39/5 21 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 1997 London gnd-content |
| genre_facet | Konferenzschrift 1997 London |
| id | DE-604.BV011497708 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T15:06:21Z |
| institution | BVB |
| institution_GND | (DE-588)2165008-1 |
| isbn | 3540634657 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007737703 |
| oclc_num | 37437546 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-384 DE-739 DE-20 DE-19 DE-BY-UBM DE-83 DE-706 |
| owner_facet | DE-91G DE-BY-TUM DE-384 DE-739 DE-20 DE-19 DE-BY-UBM DE-83 DE-706 |
| physical | XI, 503 S. Ill., graph. Darst. |
| publishDate | 1997 |
| publishDateSearch | 1997 |
| publishDateSort | 1997 |
| publisher | Springer |
| record_format | marc |
| series | Lecture notes in computer science |
| series2 | Lecture notes in computer science |
| spelling | Field programmable logic and applications 7th international workshop, FPL '97, London, UK, September 1 - 3, 1997 ; proceedings Wayne Luk ... (eds.) Field-programmable logic and applications Berlin [u.a.] Springer 1997 XI, 503 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 1304 FPGA inriac Hardware gtt Réseaux logiques programmables - Congrès ram reconfiguration inriac robotique inriac réseau logique programmable inriac traitement image inriac traitement signal inriac vidéo inriac Field programmable gate arrays -- Congresses Programmable array logic -- Congresses Gate-Array-Bauelement (DE-588)4113666-4 gnd rswk-swf Programmierbare logische Anordnung (DE-588)4076369-9 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1997 London gnd-content Programmierbare logische Anordnung (DE-588)4076369-9 s Gate-Array-Bauelement (DE-588)4113666-4 s DE-604 Luk, Wayne Sonstige oth FPL 7 1997 London Sonstige (DE-588)2165008-1 oth Lecture notes in computer science 1304 (DE-604)BV000000607 1304 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007737703&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Field programmable logic and applications 7th international workshop, FPL '97, London, UK, September 1 - 3, 1997 ; proceedings Lecture notes in computer science FPGA inriac Hardware gtt Réseaux logiques programmables - Congrès ram reconfiguration inriac robotique inriac réseau logique programmable inriac traitement image inriac traitement signal inriac vidéo inriac Field programmable gate arrays -- Congresses Programmable array logic -- Congresses Gate-Array-Bauelement (DE-588)4113666-4 gnd Programmierbare logische Anordnung (DE-588)4076369-9 gnd |
| subject_GND | (DE-588)4113666-4 (DE-588)4076369-9 (DE-588)1071861417 |
| title | Field programmable logic and applications 7th international workshop, FPL '97, London, UK, September 1 - 3, 1997 ; proceedings |
| title_alt | Field-programmable logic and applications |
| title_auth | Field programmable logic and applications 7th international workshop, FPL '97, London, UK, September 1 - 3, 1997 ; proceedings |
| title_exact_search | Field programmable logic and applications 7th international workshop, FPL '97, London, UK, September 1 - 3, 1997 ; proceedings |
| title_full | Field programmable logic and applications 7th international workshop, FPL '97, London, UK, September 1 - 3, 1997 ; proceedings Wayne Luk ... (eds.) |
| title_fullStr | Field programmable logic and applications 7th international workshop, FPL '97, London, UK, September 1 - 3, 1997 ; proceedings Wayne Luk ... (eds.) |
| title_full_unstemmed | Field programmable logic and applications 7th international workshop, FPL '97, London, UK, September 1 - 3, 1997 ; proceedings Wayne Luk ... (eds.) |
| title_short | Field programmable logic and applications |
| title_sort | field programmable logic and applications 7th international workshop fpl 97 london uk september 1 3 1997 proceedings |
| title_sub | 7th international workshop, FPL '97, London, UK, September 1 - 3, 1997 ; proceedings |
| topic | FPGA inriac Hardware gtt Réseaux logiques programmables - Congrès ram reconfiguration inriac robotique inriac réseau logique programmable inriac traitement image inriac traitement signal inriac vidéo inriac Field programmable gate arrays -- Congresses Programmable array logic -- Congresses Gate-Array-Bauelement (DE-588)4113666-4 gnd Programmierbare logische Anordnung (DE-588)4076369-9 gnd |
| topic_facet | FPGA Hardware Réseaux logiques programmables - Congrès reconfiguration robotique réseau logique programmable traitement image traitement signal vidéo Field programmable gate arrays -- Congresses Programmable array logic -- Congresses Gate-Array-Bauelement Programmierbare logische Anordnung Konferenzschrift 1997 London |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007737703&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000000607 |
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