Proceedings:
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Los Alamitos, Calif. [u.a.]
IEEE Computer Soc. Press
1996
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | NT: Test and design validity |
| Beschreibung: | XII, 951 S. Ill., graph. Darst. |
| ISBN: | 0780335406 0780335414 |
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Datensatz im Suchindex
| _version_ | 1820868198102204416 |
|---|---|
| adam_text |
INTRODUCTORY SECTION
Welcoming Message
.1
Steering Committee
.2
Technical Program Committee
.4
Technical Papers Evaluation and Selection Process
.7
1995
Paper Awards
.8
1997
Call for Papers
.9
Reviewers
.944
Author Index
.950
SESSIONI:
PLENARY
Session Chair: Ben Bennetts, Moderator: Charles Hawkins
Keynote Address
Emerging Technologies Drive Domain-Specific Solutions
Waiden (Wally)
С.
Rhines
.10
Invited Address
New and Not-So-New Test Challenges of the Next Decade
Wojciech Mały
.11
SESSION
2.0:
AUTOMATIC TEST GENERATION
Session Chair: J. Abraham, Coordinator: S. Davidson
2.1
Test Generation for Ultra-Large Circuits Using A TPG
Constraints and Test-Pattern Templates
P.
Wohl,
J. Waicukauski
.13
2.2
Test Pattern Generation for Circuits with Asynchronous
Signals Based on Scan, M. Teramoto, T. Fukazawa
.21
2.3
Accelerated Compact Test Set Generation for Three-State
Circuits, M.
Konijnenburg,
J.
van
der
Linden, A. van
de Goor.
29
2.4
Comparing
Topologica!,
Symbolic and GA-based ATPGs: An
Experimental Approach
F.
Corno,
P. Prinetto, M. Rebaudengo, M. Sonza
Reorda
.39
SESSION
3.0:
BIST: ARCHITECTURES AND GENERATORS
Session Chair. S.
Pateras,
Coordinators: B. Nadeau-Dostie, J. Beausang
3.1
BIST Fault Diagnosis in Scan-Based VLSI Environments
Y. Wu, S. Adham
.48
3.2
LFSR Reseeding as a Component of Board Level BIST
P. Trouborst
.58
3.3
Using
ILA
Testing for BIST in FPGAs
C. Stroud,
E. Lee, S. Konala, M. Abramovici
.68
3.4
An Effective BIST Scheme for Datapaths
D. Gizopoulos, A. Paschalis, Y. Zorian
.76
SESSION
4.0:
NEW TEST CONSIDERATIONS FOR MIXED-SIGNAL
DEVICES
Session Chair: K.
Lanier,
Coordinators: S. Kumar, R. Kramer
4.1
Four
Multi
Probing Test for
16
Bit DA
С
with Vertical Contact
Probe Card, S. Sasho, T.
Sakata
.86
Table of
Contents
ITC
Office
205
Tennyson Avenue, Suite
С
Altoona, PA
16602
USA
Tel: (814) 941-4666
INTERNATIONAL
TEST
CONFERENCE
1.1996
4.2
A Demonstration
1С
for the P1
149.4
Mixed-Signal Test
Standard, K. Lofstrom
.92
4.3
Testing the Digital Modulation of PHS Devices
K.
Asami
.99
SESSION
5.0:
TOPICS IN TEST HARDWARE
Session Chair: J. Woyke, Coordinator: D. Wheater
5.1
Testing and Characterizing Jitter in
1
00BASE-TX
and
155.52
Mbit/S ATM Devices with a
1
Gsample/s AWG in an ATE
System, B. Kulp
.104
5.2
High-Speed IDDQ Measurement Circuit
K. Isawa, Y. Hashimoto
.112
5.3
Extending Calibration Intervals
S.Max
.118
5.4
Manufacturing Test of Fiber Channel Communications Cards
and Optical Subassemblies, S. DeFoster, D.
Karst,
M.
Peterson, P.
Sendelbach,
К.
Kottschade
.127
SESSION
6.0:
PRACTICAL AND HIGHER-LEVEL FAULT SIMULATION
Session Chair: T. Chakraborty, Coordinator: S. Davidson
6.1
A Universal Technique for Accelerating Simulation of Scan
Test Patterns, B. Oomman, W. Cheng, J. Waicukauski
.135
6.2
On Potential Fault Detection in Sequential Circuits
E. Rudnick, J.
Patel,
I. Pomeranz
.142
6.3
Improving Gate Level Fault Coverage by
RTL
Fault Grading
W. Mao, R. Gulati
.150
6.4
Distributed Mixed Level Logic and Fault Simulation on the
Pentiunŕ
Pro Microprocessor, S. Karthik, M. Aitken,
G. Martin, S. Pappula, B. Stettler, P. Vishakantaiah,
M. d'Abreu, J. Abraham
.160
SESSION
7.0:
BIST PATTERN GENERATION
Session Chair:
С
Stroud,
Coordinators: J. Beausang, B. Nadeau-Dostie
7.1
Altering a Pseudo-Random Bit Sequence for Scan-Based
BIST,
N.
Touba, E. McCluskey
.167
7.2
MFBIST: A BIST Method for Random Pattern Resistant
Circuits, M. AlShaibi,
С
Kime.
176
7.3
Two-Dimensional Test Data Decompressor for Multiple Scan
Designs,
N.
Zacharia, J.
Rajski,
J. Tyszer, J. Waicukauski
.186
7.4
Mixed-Mode BIST Using Embedded Processors
S.
Hellebrand,
H.
Wunderlich,
Α.
Hertwig
.195
SESSION 8.0:
TESTING OF ASYNCHRONOUS CIRCUITS
Session Chair: R. Roy, Coordinator: J. Hughes
8.1
Test Quality of Asynchronous Circuits: A Defect-oriented
Evaluation, M. Roncken,
E. Bruis
.205
8.2
Optimal Scan for Pipelined Testing: An Asynchronous
Foundation, M. Roncken,
E. Aarts,
W.
Verhaegh
.215
iv
8.3
An Asynchronous Scan Path Concept for
Micropipelines
using the Bundled Data Convention
V. Schoeber, T. Kiel
.225
8.4
Synthesis-for-lnitializability of Asynchronous Sequential
Machines, M. Singh, P. Nowick
.232
Table of
Contents
SESSION
9.0:
INDUSTRY IMPACT: SCREENING, TEST, AND
MEASUREMENT BREAKTHROUGHS
Session Chair: K. Baker, Coordinator: J. Soden
9.1
Burn-in Elimination of a High Volume Microprocessor
Using /DDQ T. Henry, T.
Soo
.242
9.2
/DDQ and AC Scan: The War Against Unmodelled Defects
P. Maxwell, R. Aitken, K. Kollitz, A. Brown
.250
9.3
High Resolution IDDQ Characterization and Testing
-
Practical Issues, A. Righter, J. Soden, R. Beegle
.259
9.4
Novel Optical Probing System with
Submicron
Spatial
Resolution for Internal Diagnosis of VLSI Circuits
K. Ozaki, H. Sekiguchi, S. Wakana, Y. Goto, Y. Umehara,
J. Matsumoto
.269
SESSION
10.0:
FAULT SIMULATION AND DIAGNOSIS OF DELAY
FAULTS, Session Chair: G. Young, Coordinator: J.
Rajski
10.1
An Exact Non-Enumerative Fault Simulator for Path-Delay
Faults, M. Gharaybeh, M. Bushnell, V. Agrawal
.276
10.2
A Diagnostic ATPG for Delay Faults Based on Genetic
Algorithms, P.
Girard,
С.
Landrault,
S. Pravossoudovitch,
В.
Rodriguez
.286
10.3
Diagnostic Fault Equivalence Identification Using Redun¬
dancy Information and Structural Analysis
I. Hartanto, V. Boppana, W.
Fuchs.294
SESSION
11.0:
MEMORY TEST: DESIGN FOR TESTABILITY
Session Chair: B. Cockburn, Coordinator: T. Furuyama
11.1
Self-Learning Signature Analysis for Non-Volatile Memory
Testing, P.
Olivo,
M. Dalpasso
.303
11.2
Weak Write Test Mode: An SRAM Cell Stability Design for
Test Technique, A. Meixner, J. Banik
.309
113
A Built-in Self-Test Circuit with Timing Margin Test Function
in a
1
Gbit
Synchronous DRAM,
N.
Sakashita, F. Okuda,
K. Shimomura, H. Shimano, M. Hamada, T.
Tada, S. Komori,
К.
Kyuma, A. Yasuoka,
Η.
Abe
.319
SESSION
12.0:
BOARD TEST CHALLENGES AND SOLUTIONS
Session Chair:
A. Suto,
Coordinator: P. Pilotte
12.1
Analog/Digital Testing of Loaded Boards Without Dedicated
Test Points, C. Vaucher, L.
Balme
.325
12.2
Opens Board Test Coverage: When is
99%
Really
40%?
M. Tegethoff, K. Parker, K. Lee
.333
INTERNATIONAL
TEST
CONFERENCE
.1996
12.3
A Roadmap for Boundary-Scan Test Reuse
G. Wedge, T. Conner
.340
SESSION
13.0:
DELAY-FAULT TESTING I
Session Chair: S. Kundu, Coordinator: J.
Rajski
13.1
Local Transformations and Robust Dependent Path Delay
Faults, H.
Hengster,
U.
Sparmann,
В.
Becker,
S. Reddy
.347
13.2
On
Cancelling the Effects of
Logic
Sharing for Improved Path
Delay Fault Testability, I. Pomeranz, S. Reddy
.357
13.3
Detecting Delay Flaws by Very-Low-Voltage Testing
J. Chang, E. McCluskey
.367
SESSION
14.0:
MICROPROCESSOR TEST
Session Chair: G. Giles, Coordinator: G. Giles
14.1
Testability Features for
a Submicron
Voice-coder ASIC
F.
Pichón
.377
14.2
A BIST Methodology for Comprehensive Testing of RAM with
Reduced Heat Dissipation, H. Cheung, S. Gupta
.386
14.3
DFT Strategy for Intel Microprocessors
W. Needham,
N.
Gollakota
.396
SESSION
15.0:
AN EVOLVING MIXED-SIGNAL BOUNDARY-SCAN
STANDARD, Session Chair: K. Parker, Coordinator: P. Pilotte
15.1
Proposal to Simplify Development of a Mixed-Signal Test
Standard, L. Whetsel
.400
15.2
A Method of Extending an
1149.1
Bus for Mixed-Signal
Testing, R. Russell
.410
15.3
Early Capture for Boundary Scan Timing Measurements
K. Lofstrom
.417
SESSION
16.0:
DELAY FAULT TESTING II
Session Chair: B. Underwood, Coordinator: J.
Rajski
16.1
Identification and Test Generation for Primitive Faults
A. Krstić,
К.
Cheng,
S.
Chakradhar
.423
16.2
Test Generation for Global Delay Faults
G. Luong, D. Walker
.433
16.3
ATPD: An Automatic Test Pattern Generator for Path Delay
Faults, D. Karayiannis, S. Tragoudas
.443
SESSION
17.0:
SOFTWARE FOR NEW TEST STRATEGIES
Session Chair: H.
Ranga,
Coordinator: A. Downey
17.1
Scan Design Oriented Test Technique for VLSI's Using ATE
Y. Oyama, T. Kanai, H. Niijima
.453
17.2
Virtual Test of Noise and Jitter Parameters
K.
Helmreich,
G. Reinwardt
.461
17.3
A Novel Approach to the Analysis of VLSI Device Test
Programs,
Y. Ma, W.
Shi
.471
vi
SESSION 18.0:
INNOVATIONS
IN
CURRENT TESTING
Session Chair: P. Maxwell, Coordinators: J.
Soden, R.
Aitken
18.1
Digital Integrated Circuit Testing using Transient Signal
Analysis, J. Plusquellic, D.
Chiamili,
S.
Levitán
.481
18.2
Towards an Effective IDDQ Test Vector Selection and
Application Methodology
J. van
Sas, U.
Swerts,
M. Darquennes
.491
18.3
Correlating Defects to Functional and IDDQ Tests
T. Powell, J. Pair, B. Carbajal III
.501
SESSION
19.0:
MIXED-SIGNAL DFT AND FAULT SIMULATION
Session Chair: B. Vinnakota, Coordinator: R. Aitken
19.1
Defect-Oriented vs Schematic-Level Based Fault Simulation
for Mixed-Signal ICs
T. Olbrich, J. Perez, I. Grout, A. Richardson,
С
Ferrer
.511
19.2
Hierarchy Based Statistical Fault Simulation of Mixed-Signal
ICs, G. Devarayanadurg, P. Goteti, M.
Soma
.521
19.3
An Integration of Memory-Based Analog Signal Generation
into Current DFT Architectures
E. Hawrysh, G. Roberts
.528
SESSION
20.0:
DFT: INCHING FORWARD WITH PARTIAL-SCAN
DESIGN
Session Chair: M. Abramovici, Coordinator: D. Bhavsar
20.1
Partial Scan Design Based on State Transition Modeling
V. Boppana, W.
Fuchs.538
20.2
A Global Algorithm for the Partial Scan Design Problem
Using Circuit State Information, D. Xiang, J.
Patel
.548
20.3
Partial Scan Flip Flop Selection for Simulation-Based
Sequential ATPGs
F.
Corno,
P. Prinetto, M. Rebaudengo, M. Sonza
Reorda
.558
SESSION
21.0:
TEST LANGUAGES AND TOOLS
Session Chair: S. Raissi, Coordinator: A. Downey
21.1
Standard Test Interface Language
(STIL)
A New Language
for Patterns and Waveforms, A. Taylor,
G. Maston
.565
212
LIMSoft: Automated Tool for Design and Test Integration of
Analog Circuits
N.
Hamida, K. Saab, D.
Marche,
B. Kaminska, G. Quesnel
.571
213
Developing a Testing Maturity Model for Software Test
Process Evaluation and Improvement
I. Bumstein,
T. Suwannasart, C
Carlson
.581
SESSION
22.0:
APPLICATION OF
SPC
TO
1С
DESIGN, MANUFAC¬
TURING AND TEST
Session Chair: R. Boyle, Coordinator: E.
Hnátek
22.1
ASIC Yield Estimation at Early Design Cycle
V. Kim, M. Tegethoff, T. Chen
.590
Table of
Contents
VII
INTERNATIONAL
TEST CONFERENCE
1996
22.2
Risk Assessment Sampling Plans for Non-Standard
(Maverick) Material
D. Core
.595
22.3
SPC on
the IC-Production Test Process
J. van
der Peet,
G.
van
Boxern.605
SESSION
23.0:
NEW TECHNIQUES FOR REALISTIC FAULTS
Session Chair: P. Nigh, Coordinator: R. Aitken
23.1
Beyond the Byzantine Generals: Unexpected Behavior and
Bridging-Fault Diagnosis
D.
Lavo,
T.
Larrabee,
В.
Chess
.611
23.2
Defect-Oriented
1С
Test and Diagnosis Using VHDL Fault
Simulation
F.
Celeiro,
L.
Dias, J. Ferreira,
M.
Santos, J. Teixeira
.620
23.3
Using Target Faults to Detect Non-Target Defects
L. Wang, M. Mercer, T. Williams
.629
SESSION
24:
DESIGN-FOR-TESTABILITY INSPIRATIONS
Chair: E. McCluskey, Coordinator: D. Bhavsar
24.1
A Unifying Methodology for Intellectual Property and Custom
Logic Testing, S. Bhatia, T. Gheewala, P.
Varma
.639
24.2
Constructive Multi-Phase Test Point Insertion for
Scan-Based BIST,
N.
Tamarapalli, J.
Rajski
.649
24.3
Orthogonal Scan: Low-Overhead Scan for Data Paths
R. Norwood, E. McCluskey
.659
SESSION
25.0:
HIGH FREQUENCY AND TIMING IN ATE
Session Chair: M. Mydill, Coordinator: D. Wheater
25.1
An Application of Photoconductive Switch for High-Speed
Testing,
K. Chihara, T. Sekino, K.
Sasaki
.669
25.2
Generation Technique of 500MHz Ultra-High Speed
Algorithmic Pattern
H.
Imada,
К.
Fujisaki,
T. Ohsawa, M. Tsuto
.677
25.3
The Effect of Period Generation Techniques on Period
Resolution and Waveform Jitter in VLSI Test Systems
M. Davis
.685
SESSION
26.0:
TOPICS IN TEST ENGINEERING
Session Chair: A. Downey, Coordinator: S. Raissi
26.1
Analysis and Detection of Timing Failures in an Experimental
Test Chip, P. Franco, S. Ma, J. Chang,
Y. Chu, S.
Wattal, E.
McCluskey,
R.
Stokes,
W. Farwell
.691
26.2
A Unique Methodology for At-Speed Test of cDSP™ and
ASIC Devices, D. Potts, R. Griesmer
.701
26.3
Cost Effective Frequency Measurement for Production
Testing, R.
Stoffels
.708
VIII
SESSION 27.0: SYSTEM TEST:
PRACTICAL ASPECTS, PARTITION¬
ING AND SIMULATION
Session Chair:
С
Gloster, Coordinator: K. Komegay
27.1
Backplane Interconnect Test in a Boundary-Scan
Environment, W. Ke
.717
27.2
Testability-Oriented Hardware/Software Partitioning
Y. Le
Traon, G. Al-Hayek,
С
Robach.725
27.3
System Level Fault Simulation
P. Sanchez, I. Hidalgo
.732
SESSION
28.0:
TEST SYNTHESIS SOLUTIONS
Session Chair: S. Chakradhar,
Coordinators: K. Cheng, J. Beausang
28.1
ASIC BIST Synthesis: A VHDL Approach
T.
Eberle,
R.
McVay,
С.
Meyers,
J.
Moore
.741
28.2
Integrating Scan into Hierarchical Synthesis Methodologies
J. Beausang,
С
Elüngham,
M.
Robinson
.751
28.3
Synthesis of Self-Testing Finite State Machines from High-
Level Specifications, V. Agrawal, R. Blanton, M. Damiani
.757
SESSION
29.0:
ADVANCED FAULT MODELLING TECHNIQUES
Session Chair: K. Butler, Coordinator: J. Soden
29.1
Fault Coverage Analysis for Physically-Based CMOS Bridg¬
ing Faults at Different Power Supply Voltages
Y. Liao, D.Walker
.767
29.2
Realistic-Faults Mapping Scheme for the Fault Simulation of
Integrated Analogue CMOS Circuits, M. Ohletz
.776
29.3
lDDQTest: Sensitivity Analysis of Scaling
T. Williams, R. Dennard, R. Kapur, M. Mercer, W. Maly
.786
SESSION
30.0:
TEST ECONOMIC ISSUES
Session Chair: M. Abadir, Coordinator: A. Ambler
30.1
Effects of Multi-Product, Small-Sized Production of LSIs
Packaged in Various Packages on the Final Test Process
Efficiency and Cost, H.
Fujioka, K.
Nakamae, A. Higashi
.793
30.2
Issues In Optimizing the Test Process
-
A Telecom Case
Study, F. Frayman, M. Tegethoff, B. White
.800
30.3
Application of Boundary Scan in a Fault Tolerant Computer
System, M. Boutin, P.
Dziel
.809
SESSION
31.0:
MCM
TEST: METHODS AND APPLICATIONS
Session Chair: Y. Zorian, Coordinator: D. Keezer
31.1
Optimal Multiple Chain Relay Testing Scheme for MCMs on
Large Area Substrates, K. Sasidhar, A. Chatterjee, Y. Zorian
. 818
312
Three Different MCMs, Three Different Test Strategies
A. Flint
.828
313
MCM
Compute Node Thermal Failure
-
Design or Test
Problem?, E. Sayre
.834
Table of
Contents
IX
INTERNATIONAL
TEST
CONFERENCE
J996
SESSION D1.O:
DESIGN
VALIDATION:
METHODOLOGIESAND
CASE
STUDIES
Session Chair: D. Fujita, Coordinator:
S. Dey
D1.1 Commercial Design Verification: Methodology and Tools
С
Pixley,
N.
Strader, W. Bruce, J. Park, M.
Kaufmann,
К.
Shultz,
M.
Burns,
J.
Kumar,
J.
Yuan,
J.
Nguyen
.839
D1.2 Formal Verification of the UltraSPARC™ Family of
Processors via ATPG Methods, M. Levitt
.849
D1.3 PowerPC™ Array Verification Methodology using Formal
Techniques,
N.
Ganguly, M. Abadir, M. Pandey
.857
SESSION D2.0: HYBRID VALIDATION AND TEST TECHNIQUES
Session Chair: J.
Patel,
Coordinator:
S. Dey
D2.
1
An ATPG-Based Framework for Verifying Sequential
Equivalence, S. Huang, K. Cheng, K. Chen, U. Glaeser
.865
D2.2 A Unified Framework for Design Validation and
Manufacturing Test, D. Moundanos, J. Abraham, Y. Hoskote
. 875
D2.3 From Specification Validation to Hardware Testing: A Unified
Method, G. Al-Hayek,
С
Robach.885
SESSION D3.0: DESIGN VALIDATION: FROM SYSTEM
SPECIFICATION TO PROCESS EFFECTS
Session Chair: V. Agrawal, Coordinator:
S. Dey
D3.
1
Testing-Based Analysis of
Real-Time
System Models
D. Clarke, I. Lee
.894
D3.2 Generation of Test Cases for Hardware Design Verification
of a Super-Scalar Fetch Processor
I. Pomeranz,
N.
Saxena, R. Reeve, P.
Kulkami,
Y.
Li
.904
D3.3 Process-Aggravated Noise (PAN): New Validation and Test
Problems, M.
Breuer,
S.
Gupta
.914
SESSION L1: UNPOWERED OPENS TESTING
Session Chair: W. Mann, Coordinator: K. Parker
Introduction
ITC 1996
Lecture Series on Unpowered Opens
Testing, K. Parker
.924
L1.1
Capacitive
Leadframe Testing
T. Turner
.925
L1.2 High Fault Coverage of In-Circuit
1С
Pin Faults with a
Vectohess Test Technique Using Parasitic Transistors
J. Ferguson
.926
L1.3&5 Two New Techniques for Identifying Opens on Printed
Circuit Boards: Analog Junction Test, and Radio Frequency
Induction Test, J. Wrinn
.927
L
1.4
Analog AC Harmonic Method for Detecting Solder Opens
A. Suto
.928
L1.7 Unpowered Opens Test with
Х
-Ray Laminography
S. Oresjo
.929
SESSION L2:
PRACTICAL ASPECTS OF
1С
DIAGNOSIS
&
FAILURE
ANALYSIS: A WALK THROUGH THE PROCESS
Session Chair: D. Vallett, Coordinators: J.
Soden, E.
Hnátek
L2.
1
An Overview of CMOS VLSI Failure Analysis and the
Importance of Test and Diagnostics
D. Vallett
.930
L2.
2
Modelling the Unmodellable: Algorithmic Fault Diagnosis
R. Aitken
.931
L2.3 Shmoo Plots
-
the Black Art of
1С
Test
K. Baker, J. van Beers
.932
12.4
Integrating Automated Diagnosis into the Testing and Failure
Analysis Operations
K. Butler, K. Johnson, J.
Platt,
A. Jones, J. Saxena
.934
L2.5
1С
Failure Analysis Tools and Techniques
-
Magic, Mystery,
and Science, J. Soden, R. Anderson,
С
Henderson
.935
L2.
6
Practical Issues of Failure Diagnosis and Analysis in a Fast
Cycle Time Environment, D. Staab
.936
Table of
Contents
PANEL
1 :
WHY DO WE TALK ABOUT DFT WHEN THE PROBLEM IS
BAD DESIGN AND BAD CAD TOOLS?
Organizer and Moderator: T. Ambler
P1.2 The Key to Concurrent Engineehng is Design Tools
W. Simpson
.937
PANEL
2:
ASYNCHRONOUS DESIGN: NIGHTMARE OR
OPPORTUNITY?
Moderator: E, McCluskey, Organizer:
E. Bruis
P2.2 The Return of Asynchronous Logic
S. Furber
.938
P2.3 Asynchronous Design: Working the Fast Lane
M. Roncken
.939
PANEL
5:
DFT FOR EMBEDDED CORES
Moderator: S. Hemmady, Organizers: T. Anderson, Y. Zorian
P5.2 Challenge of the 90's: Testing CoreWare™ Based ASICs
R. Rajsuman
.940
PANEL
6:
WHAT ARE THE NEXT GENERATION TEST
METHODOLOGIES FOR BOARD AND SYSTEM TEST?
Moderator: D. Sterba, Organizer:
N.
Doherty
P6.3 The Need for Complete System Level Test Standardization
P.
Dziel
.941
PANEL
7:
WILL IDDQ TESTING LEAK AWAY IN DEEP SUB-MICRON
TECHNOLOGY?
Moderator: E. McCluskey, Organizer: K. Baker
P7.3 Deep Sub-micron IDDQ Test Options
M. Sachdev
.942
XI |
| any_adam_object | 1 |
| author_corporate | International Test Conference Washington, DC |
| author_corporate_role | aut |
| author_facet | International Test Conference Washington, DC |
| author_sort | International Test Conference Washington, DC |
| building | Verbundindex |
| bvnumber | BV011362811 |
| classification_rvk | ZN 4030 |
| classification_tum | ELT 359f |
| ctrlnum | (OCoLC)634748018 (DE-599)BVBBV011362811 |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre_facet | Konferenzschrift 1996 Washington DC |
| id | DE-604.BV011362811 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T13:20:33Z |
| institution | BVB |
| institution_GND | (DE-588)5244583-5 |
| isbn | 0780335406 0780335414 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007636889 |
| oclc_num | 634748018 |
| open_access_boolean | |
| owner | DE-739 DE-91G DE-BY-TUM DE-91 DE-BY-TUM DE-29T DE-83 |
| owner_facet | DE-739 DE-91G DE-BY-TUM DE-91 DE-BY-TUM DE-29T DE-83 |
| physical | XII, 951 S. Ill., graph. Darst. |
| publishDate | 1996 |
| publishDateSearch | 1996 |
| publishDateSort | 1996 |
| publisher | IEEE Computer Soc. Press |
| record_format | marc |
| spelling | International Test Conference 27 1996 Washington, DC Verfasser (DE-588)5244583-5 aut Proceedings International Test Conference 1996 Test and design validity Los Alamitos, Calif. [u.a.] IEEE Computer Soc. Press 1996 XII, 951 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier NT: Test and design validity Mikroelektronik (DE-588)4039207-7 gnd rswk-swf Bildverstehen (DE-588)4202022-0 gnd rswk-swf Testen (DE-588)4367264-4 gnd rswk-swf Elektronik (DE-588)4014346-6 gnd rswk-swf Computerunterstütztes Verfahren (DE-588)4139030-1 gnd rswk-swf Computersimulation (DE-588)4148259-1 gnd rswk-swf Mustererkennung (DE-588)4040936-3 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Maschinelles Sehen (DE-588)4129594-8 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Datenverarbeitungssystem (DE-588)4125229-9 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Telekommunikation (DE-588)4059360-5 gnd rswk-swf Medizin (DE-588)4038243-6 gnd rswk-swf Prüftechnik (DE-588)4047610-8 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1996 Washington DC gnd-content Integrierte Schaltung (DE-588)4027242-4 s Prüftechnik (DE-588)4047610-8 s DE-604 Datenverarbeitungssystem (DE-588)4125229-9 s Computersimulation (DE-588)4148259-1 s 1\p DE-604 Telekommunikation (DE-588)4059360-5 s 2\p DE-604 Mikroelektronik (DE-588)4039207-7 s 3\p DE-604 Elektronik (DE-588)4014346-6 s Testen (DE-588)4367264-4 s 4\p DE-604 VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s 5\p DE-604 Computerunterstütztes Verfahren (DE-588)4139030-1 s Medizin (DE-588)4038243-6 s 6\p DE-604 7\p DE-604 Bildverstehen (DE-588)4202022-0 s Maschinelles Sehen (DE-588)4129594-8 s 8\p DE-604 Mustererkennung (DE-588)4040936-3 s 9\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007636889&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 5\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 6\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 7\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 8\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 9\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Proceedings Mikroelektronik (DE-588)4039207-7 gnd Bildverstehen (DE-588)4202022-0 gnd Testen (DE-588)4367264-4 gnd Elektronik (DE-588)4014346-6 gnd Computerunterstütztes Verfahren (DE-588)4139030-1 gnd Computersimulation (DE-588)4148259-1 gnd Mustererkennung (DE-588)4040936-3 gnd Entwurf (DE-588)4121208-3 gnd Maschinelles Sehen (DE-588)4129594-8 gnd VLSI (DE-588)4117388-0 gnd Datenverarbeitungssystem (DE-588)4125229-9 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Telekommunikation (DE-588)4059360-5 gnd Medizin (DE-588)4038243-6 gnd Prüftechnik (DE-588)4047610-8 gnd |
| subject_GND | (DE-588)4039207-7 (DE-588)4202022-0 (DE-588)4367264-4 (DE-588)4014346-6 (DE-588)4139030-1 (DE-588)4148259-1 (DE-588)4040936-3 (DE-588)4121208-3 (DE-588)4129594-8 (DE-588)4117388-0 (DE-588)4125229-9 (DE-588)4027242-4 (DE-588)4059360-5 (DE-588)4038243-6 (DE-588)4047610-8 (DE-588)1071861417 |
| title | Proceedings |
| title_alt | Test and design validity |
| title_auth | Proceedings |
| title_exact_search | Proceedings |
| title_full | Proceedings International Test Conference 1996 |
| title_fullStr | Proceedings International Test Conference 1996 |
| title_full_unstemmed | Proceedings International Test Conference 1996 |
| title_short | Proceedings |
| title_sort | proceedings |
| topic | Mikroelektronik (DE-588)4039207-7 gnd Bildverstehen (DE-588)4202022-0 gnd Testen (DE-588)4367264-4 gnd Elektronik (DE-588)4014346-6 gnd Computerunterstütztes Verfahren (DE-588)4139030-1 gnd Computersimulation (DE-588)4148259-1 gnd Mustererkennung (DE-588)4040936-3 gnd Entwurf (DE-588)4121208-3 gnd Maschinelles Sehen (DE-588)4129594-8 gnd VLSI (DE-588)4117388-0 gnd Datenverarbeitungssystem (DE-588)4125229-9 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Telekommunikation (DE-588)4059360-5 gnd Medizin (DE-588)4038243-6 gnd Prüftechnik (DE-588)4047610-8 gnd |
| topic_facet | Mikroelektronik Bildverstehen Testen Elektronik Computerunterstütztes Verfahren Computersimulation Mustererkennung Entwurf Maschinelles Sehen VLSI Datenverarbeitungssystem Integrierte Schaltung Telekommunikation Medizin Prüftechnik Konferenzschrift 1996 Washington DC |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007636889&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT internationaltestconferencewashingtondc proceedings AT internationaltestconferencewashingtondc testanddesignvalidity |