Practical formal methods for hardware design:
Gespeichert in:
| Format: | Buch |
|---|---|
| Sprache: | German |
| Veröffentlicht: |
Berlin [u.a.]
Springer
1997
|
| Schriftenreihe: | Research reports ESPRIT
Project 6128, FORMAT ; 1 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XIV, 293 S. graph. Darst. |
| ISBN: | 3540620079 |
Internformat
MARC
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| 084 | |a 28 |2 sdnb | ||
| 245 | 1 | 0 | |a Practical formal methods for hardware design |c C. Delgado Kloos ; W. Damm (ed.) |
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 1997 | |
| 300 | |a XIV, 293 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Research reports ESPRIT : Project 6128, FORMAT |v 1 | |
| 650 | 4 | |a Digital integrated circuits -- Design and construction -- Methodology | |
| 650 | 4 | |a Logic circuits -- Design and construction -- Methodology | |
| 650 | 4 | |a Computer hardware description languages | |
| 650 | 4 | |a Formal methods (Computer science) | |
| 650 | 0 | 7 | |a Formale Sprache |0 (DE-588)4017848-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Spezifikationssprache |0 (DE-588)4182217-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurfsautomation |0 (DE-588)4312536-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a Entwurfsautomation |0 (DE-588)4312536-0 |D s |
| 689 | 0 | 2 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 0 | 3 | |a Spezifikationssprache |0 (DE-588)4182217-1 |D s |
| 689 | 0 | 4 | |a Formale Sprache |0 (DE-588)4017848-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Delgado Kloos, Carlos |e Sonstige |0 (DE-588)1028939744 |4 oth | |
| 830 | 0 | |a Research reports ESPRIT |v Project 6128, FORMAT ; 1 |w (DE-604)BV014046304 |9 1 | |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007609173&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007609173 | |
Datensatz im Suchindex
| _version_ | 1807773539142467584 |
|---|---|
| adam_text |
TABLE
OF
CONTENTS
PREFACE
MIKE
NEWMAN
.
V
INTRODUCTION
CARLOS
DELGADO
KLOOS,
WERNER
DAMM,
AND
JUAN
GOICOLEA
.
1
1.
FORMAL
METHODS
VS.
CONVENTIONAL
ONES
.
1
2.
THE
FORMAT
PROJECT
.
2
3.
ORGANIZATION
OF
THIS
BOOK
.
3
PART
I.
OVERVIEW
DESIGN
METHODOLOGY
FOR
COMPLEX
VLSI
DEVICES
MASSIMO
BOMBANA
AND
FABRIZIO
FERRANDI
.
7
1.
INTRODUCTION:
NEEDS
AND
CONSTRAINTS
OF
THE
ESDA
MARKET
.
7
2.
THE
DESIGN
FLOW
.
10
2.1
DESIGN
SPECIFICATION
AND
DOCUMENTATION
.
11
2.2
VHDL
FOR
SIMULATION
AND
SYNTHESIS
.
13
2.3
FROM
SPECIFICATION
TO
IMPLEMENTATION
.
14
3.
DESIGN
CAPTURE
WITH
VHDL/S
.
16
4.
THE
FORMAT
METHODOLOGY
AT
WORK
.
18
5.
CONCLUDING
REMARKS
.
22
SPECIFICATION
LANGUAGES
WERNER
DAMM,
GERT
DBHMEN,
JOHANNES
HELBIG,
PETER
KELB,
RAINER
SCHLBR,
WERNER
GRASS,
CHRISTIAN
GROBE,
STEFAN
LENK,
AND
WOLF-DIETER
TIEDEMANN
.
23
1.
VHDL/S
.
23
2.
STATE
BASED
SPECIFICATIONS
.
25
2.1
INTEGRATION
.
27
2.2
A
DESIGN
SITUATION
.
28
3.
TIMING
DIAGRAMS
.
.
31
3.1
SYNTAX
DEFINITION
.
32
3.2
INFORMAL
SEMANTICS
.
36
4.
EXAMPLE:
A
TRAFFIC
LIGHT
SYSTEM
.
42
4.1
STRUCTURE
OF
THE
TRAFFIC
LIGHT
SYSTEM
.
42
4.2
BEHAVIOURAL
DESCRIPTION
OF
THE
TRAFFIC
LIGHT
SYSTEM
.
44
5.
TIMING
DIAGRAM
DESCRIPTION
.
47
6.
SUMMARY
.
50
VERIFICATION
FLOW
WERNER
DAMM,
GERT
DOHMEN,
RONALD
HERRMANN,
PETER
KELB,
HERGEN
PARGMANN,
AND
RAINER
SCHLOR
.
52
1.
VERIFICATION
TOOLS
.
52
2.
PROOF
MANAGER
.
55
2.1
PURPOSE
OF
THE
PROOF
MANAGER
.
55
2.2
VERIFICATION
OF
BEHAVIOURAL
DESCRIPTIONS
.
56
2.3
HANDLING
HIERARCHICAL
STRUCTURES
.
60
3.
PROOF
STEPS
FOR
THE
TRAFFIC
LIGHT
SYSTEM
.
63
4.
COMPOSITIONAL
VERIFICATION
.
65
5.
COMPONENT
VERIFICATION
.
70
5.1
INTRODUCTION
.
70
5.2
VERIFICATION
OF
THE
TRAFFIC
LIGHT
CONTROLLER
.
72
6.
GENERATION
OF
TEMPORAL
LOGIC
.
77
7.
SUMMARY
.
80
SYNTHESIS
FLOW
WERNER
GRASS,
WOLF-DIETER
TIEDEMANN,
CARLOS
DELGADO
KLOOS,
AND
ANDRES
MARIN
LOPEZ
.
81
1.
INTRODUCTION
.
81
2.
DESIGN
FLOW
.
82
3.
TIMING
DIAGRAMS
AS
SPECIFICATIONS
.
83
4.
T-LOTOS
SEMANTICS
OF
TIMING
DIAGRAMS
.
84
4.1
FORMALIZATION
OF
TIMING
DIAGRAM
SPECIFICATIONS
.
85
4.2
TIMED
GRAPHS
AS
INTERNAL
REPRESENTATION
.
86
5.
THE
DIFFERENT
WAYS
OF
PRODUCING
T-LOTOS
IMPLEMENTATION
DESCRIP
TIONS
.
87
5.1
AUTOMATIC
TRANSFORMATION
.
87
5.2
INTERACTIVE
TRANSFORMATION
.
87
6.
TRANSLATION
FROM
T-LOTOS
TO
VHDL
.
91
6.1
TRANSLATION
PROCESS
.
91
6.2
VHDL
PRODUCED
.
94
7.
CONCLUSION
.
96
PART
II.
INDUSTRIAL
EXPERIENCE
.
.
'
J
'
APPLICATION
OF
A
FORMAL
VERIFICATION
TOOLSET
TO
THE
DESIGN
OF
INTEGRATED
CIRCUITS
IN
AN
INDUSTRIAL
ENVIRONMENT
PIERRE
PLAZA,
JOSE
LUIS
CONESA,
AND
FERNANDO
PALAO
.
99
1.
INTRODUCTION
.
99
2.
DESCRIPTION
OF
THE
DEPTH
CIRCUIT
.
100
2.1
DEPTH
INTERFACE
WITH
THE
ENVIRONMENT
.
101
2.2
ARCHITECTURE
.
101
2.3
CONSIDERATIONS
AND
DECISIONS
REGARDING
FORMAT
.
105
3.
INTEGRATION
OF
THE
FORMAT
TOOLS
INTO
THE
TELEFONICA
I+D
DESIGN
PROCESS
.
106
3.1
SYSTEM
SPECIFICATION
.
107
3.2
SYNTHESIS
TOOLS
.
109
3.3
VERIFICATION
TOOLS
.
109
4.
WORKING
METHODOLOGY
AND
RESULTS
.
110
4.1
THE
SYNTHESIS
LINE
.
110
4.2
THE
VERIFICATION
LINE
.
118
5.
CONCLUSIONS
.
130
ITALTEL
APPLICATION
OF
THE
FORMAT
DESIGN
FLOW
MASSIMO
BOMBANA,
PATRIZIA
CAVALLORO,
FABRIZIO
FERRANDI,
AND
FERNANDA
SALICE
.
132
1.
INTRODUCTION
.
132
2.
DEVICE
SPECIFICATION
IN
VHDL/S
.
133
2.1
DESIGN
CAPTURE
.
134
3.
THE
VERIFICATION
FLOW
.
137
3.1
DESIGN
PROPERTIES
.
140
3.2
USERS
'
FEEDBACK
.
144
4.
THE
SYNTHESIS
FLOW
.
146
4.1
FROM
TIMING
DIAGRAMS
TO
VHDL
.
146
4.2
USING
THE
STRUCTURIZER
.
151
5.
EXAMPLE
OF
FORMAT
TOOLS
ENCAPSULATION
INTO
A
FRAMEWORK
.
155
6.
CONCLUSION
.
158
SIEMENS
INDUSTRIAL
EXPERIENCE
RONALD
HERRMANN,
JORG
BORMANN,
THOMAS
FILKORN,
JORG
LOHSE,
AND
HANS-ALBERT
SCHNEIDER
.
159
1.
DESIGN
FLOW
AND
VERIFICATION
METHODOLOGY
.
159
2.
APPLICATION
REPORTS
.
161
2.1
VERIFICATION
OF
A
TOKEN
RING
CONTROLLER
.
161
2.2
VERIFICATION
OF
AN
ARBITER
.
163
2.3
VERIFICATION
OF
A
SERIAL
V24
INTERFACE
CONTROLLER
.
166
2.4
VERIFICATION
OF
AN
ATM
COMPONENT
.
167
2.5
VERIFICATION
OF
A
FIFO
BUFFER
COMPONENT
.
169
3.
CONCLUSION
.
171
PART
III.
TECHNICAL
BACKGROUND
THE
FORMAT
MODEL
CHECKER
ANDREAS
SCHOLZ,
THOMAS
FILKORN,
JORG
LOHSE,
HANS-ALBERT
SCHNEIDER,
ERIK
TIDEN,
AND
PETER
WARKENTIN
.
175
1.
INTRODUCTION
.
175
2.
ARCHITECTURE
.
176
2.1
INTERFACES
.
176
2.2
THE
ALGORITHM
.
178
3.
THE
CHECKING
COMPONENT
.
178
4.
THE
DEBUGGING
COMPONENT
.
178
5.
THE
TAUTOLOGY
CHECKER
.
182
REASONING
NICK
CHAPMAN,
SIMON
FINN,
AND
MICHAEL
P.
FOURMAN
.
184
1.
LAMBDA
-
A
BEHAVIOURAL
DESIGN
TOOL
.
184
1.1
THE
LAMBDA
LOGIC
.
185
1.2
PROOF
IN
LAMBDA
.
186
2.
GENERATING
L2
SPECIFICATIONS
.
188
2.1
MODELLING
VHDL
IN
L2
.
188
3.
TUTORIAL
EXAMPLES
.
202
3.1
SIMPLE
REASONING
.
202
3.2
RECURSIVE
DEFINITIONS
.
206
3.3
ARRAYS
.
211
4.
CONCLUSIONS
.
216
VHDL
FORMAL
MODELING
AND
ANALYSIS
LUIS
ENTRENA,
SERAFIN
OLCOZ,
AND
JUAN
GOICOLEA
.
217
1.
INTRODUCTION
.
217
2.
A
FORMAL
MODEL
OF
VHDL
.
217
3.
PETRI
NETS
AND
VHDL
ANALYSIS
.
220
3.1
PETRI
NET
ANALYSIS
.
220
3.2
MOTIVATION
OF
STRUCTURAL
ANALYSIS
TECHNIQUES
.
222
3.3
VHDL
ANALYSIS
.
222
4.
CONCLUSIONS
.
227
SYNTHESIS
TECHNIQUES
WOLF-DIETER
TIEDEMANN,
STEFAN
LENK,
CHRISTIAN
GROBE,
WERNER
GRASS,
CARLOS
DELGADO
KLOOS,
ANDRES
MARIN
LOPEZ,
TOMAS
DE
MIGUEL
MORO,
AND
TOMAS
ROBLES
VALLADARES
.
229
1.
INTRODUCTION
.
229
2.
T-LOTOS
.
230
2.1
SYNTAX
OF
T-LOTOS
.
231
2.2
T-LOTOS
OPERATIONAL
SEMANTICS
.
233
2.3
EXAMPLES
OF
SPECIFICATIONS
IN
T-LOTOS
.
234
2.4
TIMED
GRAPHS
AS
INTERNAL
REPRESENTATION
.
236
3.
FORMALIZING
TIMING
DIAGRAMS
.
242
3.1
GENERAL
TRANSLATION
APPROACH
.
242
3.2
TRANSLATION
OF
GRAPHICAL
PRIMITIVES
.
244
3.3
THE
OPERATIONAL
MODEL
.
247
4.
AUTOMATIC
SYNTHESIS
.
248
5.
INTERACTIVE
SYNTHESIS
.
249
5.1
THE
SYNTHESIS
ALGORITHM
.
250
5.2
IMPLEMENTATION
RELATION
.
251
5.3
PROTOCOL
CONVERSION
.
254
5.4
AN
EXAMPLE:
A
FREQUENCY
COUNTER
.
256
6.
CONCLUSIONS
.
263
GENERATING
VHDL
CODE
FROM
LOTOS
DESCRIPTIONS
ANDRES
MARIN
LOPEZ,
CARLOS
DELGADO
KLOOS,
TOMAS
ROBLES
VALLADARES,
AND
TOMAS
DE
MIGUEL
MORO
.
266
1.
INTRODUCTION
.
266
2.
TRANSLATION
OF
T-LOTOS
TO
VHDL
.
267
2.1
RELATION
BETWEEN
LOTOS
AND
VHDL
SEMANTIC
ELEMENTS
.
269
2.2
RESTRICTIONS
IMPOSED
BY
THE
TRANSLATION
.
271
2.3
TRANSLATION
SCHEME
.
272
2.4
OPTIMIZING
THE
CODE
.
275
3.
DESIGN
OF
AN
ETHERNET
BRIDGE
.
275
4.
SYSTEM
TESTING
.
283
4.1
DERIVATION
AND
VALIDATION
OF
TEST
CASES
.
284
4.2
TEST
SUITE
APPLICATION
.
285
5.
TESTING
ENVIRONMENT
.
287
5.1
TEST
CASE
PRODUCTION
.
289
5.2
TEST
CASES
IMPLEMENTATION
.
290
5.3
TEST
CASE
EXECUTION
AND
REPORT
PRODUCTION
.
291
6.
CONCLUSION
.
292 |
| any_adam_object | 1 |
| author_GND | (DE-588)1028939744 |
| building | Verbundindex |
| bvnumber | BV011324786 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874.65.P73 1997 |
| callnumber-search | TK7874.65.P73 1997 |
| callnumber-sort | TK 47874.65 P73 41997 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 150 ST 190 ST 195 |
| classification_tum | DAT 190f |
| ctrlnum | (OCoLC)36883954 (DE-599)BVBBV011324786 |
| dewey-full | 621.39/2 621.39/221 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/2 621.39/2 21 |
| dewey-search | 621.39/2 621.39/2 21 |
| dewey-sort | 3621.39 12 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV011324786 |
| illustrated | Illustrated |
| indexdate | 2024-08-19T00:26:31Z |
| institution | BVB |
| isbn | 3540620079 |
| language | German |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007609173 |
| oclc_num | 36883954 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-739 DE-384 DE-521 |
| owner_facet | DE-91G DE-BY-TUM DE-739 DE-384 DE-521 |
| physical | XIV, 293 S. graph. Darst. |
| publishDate | 1997 |
| publishDateSearch | 1997 |
| publishDateSort | 1997 |
| publisher | Springer |
| record_format | marc |
| series | Research reports ESPRIT |
| series2 | Research reports ESPRIT : Project 6128, FORMAT |
| spelling | Practical formal methods for hardware design C. Delgado Kloos ; W. Damm (ed.) Berlin [u.a.] Springer 1997 XIV, 293 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Research reports ESPRIT : Project 6128, FORMAT 1 Digital integrated circuits -- Design and construction -- Methodology Logic circuits -- Design and construction -- Methodology Computer hardware description languages Formal methods (Computer science) Formale Sprache (DE-588)4017848-1 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Spezifikationssprache (DE-588)4182217-1 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Entwurfsautomation (DE-588)4312536-0 s VHDL (DE-588)4254792-1 s Spezifikationssprache (DE-588)4182217-1 s Formale Sprache (DE-588)4017848-1 s DE-604 Delgado Kloos, Carlos Sonstige (DE-588)1028939744 oth Research reports ESPRIT Project 6128, FORMAT ; 1 (DE-604)BV014046304 1 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007609173&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Practical formal methods for hardware design Research reports ESPRIT Digital integrated circuits -- Design and construction -- Methodology Logic circuits -- Design and construction -- Methodology Computer hardware description languages Formal methods (Computer science) Formale Sprache (DE-588)4017848-1 gnd VHDL (DE-588)4254792-1 gnd Spezifikationssprache (DE-588)4182217-1 gnd Entwurfsautomation (DE-588)4312536-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4017848-1 (DE-588)4254792-1 (DE-588)4182217-1 (DE-588)4312536-0 (DE-588)4117388-0 |
| title | Practical formal methods for hardware design |
| title_auth | Practical formal methods for hardware design |
| title_exact_search | Practical formal methods for hardware design |
| title_full | Practical formal methods for hardware design C. Delgado Kloos ; W. Damm (ed.) |
| title_fullStr | Practical formal methods for hardware design C. Delgado Kloos ; W. Damm (ed.) |
| title_full_unstemmed | Practical formal methods for hardware design C. Delgado Kloos ; W. Damm (ed.) |
| title_short | Practical formal methods for hardware design |
| title_sort | practical formal methods for hardware design |
| topic | Digital integrated circuits -- Design and construction -- Methodology Logic circuits -- Design and construction -- Methodology Computer hardware description languages Formal methods (Computer science) Formale Sprache (DE-588)4017848-1 gnd VHDL (DE-588)4254792-1 gnd Spezifikationssprache (DE-588)4182217-1 gnd Entwurfsautomation (DE-588)4312536-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Digital integrated circuits -- Design and construction -- Methodology Logic circuits -- Design and construction -- Methodology Computer hardware description languages Formal methods (Computer science) Formale Sprache VHDL Spezifikationssprache Entwurfsautomation VLSI |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007609173&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV014046304 |
| work_keys_str_mv | AT delgadoklooscarlos practicalformalmethodsforhardwaredesign |