ESD in silicon integrated circuits:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Chichester [u.a.]
Wiley
1996
|
| Ausgabe: | Repr. |
| Schriftenreihe: | Design and measurement in electronic engineering
|
| Schlagworte: | |
| Beschreibung: | XIV, 209 S. graph. Darst. |
| ISBN: | 0471954810 |
Internformat
MARC
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| 003 | DE-604 | ||
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| 007 | t | ||
| 008 | 970225s1996 d||| |||| 00||| eng d | ||
| 020 | |a 0471954810 |9 0-471-95481-0 | ||
| 035 | |a (OCoLC)246078911 | ||
| 035 | |a (DE-599)BVBBV011220023 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
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| 084 | |a ZN 4900 |0 (DE-625)157417: |2 rvk | ||
| 084 | |a ELT 249f |2 stub | ||
| 100 | 1 | |a Amerasekera, Ajith |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a ESD in silicon integrated circuits |c Ajith Amerasekera ; Charvaka Duvvury |
| 250 | |a Repr. | ||
| 264 | 1 | |a Chichester [u.a.] |b Wiley |c 1996 | |
| 300 | |a XIV, 209 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Design and measurement in electronic engineering | |
| 650 | 4 | |a Electrostatics | |
| 650 | 4 | |a Integrated circuits |x Protection | |
| 650 | 4 | |a Semiconductors | |
| 650 | 4 | |a Semiconductors |x Protection | |
| 650 | 4 | |a Static eliminators | |
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Elektrostatische Entladung |0 (DE-588)4401020-5 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
| 689 | 0 | 1 | |a Elektrostatische Entladung |0 (DE-588)4401020-5 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Duvvury, Charvaka |e Verfasser |4 aut | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-007527556 | ||
Datensatz im Suchindex
| _version_ | 1804125718622240768 |
|---|---|
| any_adam_object | |
| author | Amerasekera, Ajith Duvvury, Charvaka |
| author_facet | Amerasekera, Ajith Duvvury, Charvaka |
| author_role | aut aut |
| author_sort | Amerasekera, Ajith |
| author_variant | a a aa c d cd |
| building | Verbundindex |
| bvnumber | BV011220023 |
| classification_rvk | ZN 4900 |
| classification_tum | ELT 249f |
| ctrlnum | (OCoLC)246078911 (DE-599)BVBBV011220023 |
| dewey-full | 621.38152 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.38152 |
| dewey-search | 621.38152 |
| dewey-sort | 3621.38152 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | Repr. |
| format | Book |
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| id | DE-604.BV011220023 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:06:01Z |
| institution | BVB |
| isbn | 0471954810 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007527556 |
| oclc_num | 246078911 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-29T |
| owner_facet | DE-91 DE-BY-TUM DE-29T |
| physical | XIV, 209 S. graph. Darst. |
| publishDate | 1996 |
| publishDateSearch | 1996 |
| publishDateSort | 1996 |
| publisher | Wiley |
| record_format | marc |
| series2 | Design and measurement in electronic engineering |
| spelling | Amerasekera, Ajith Verfasser aut ESD in silicon integrated circuits Ajith Amerasekera ; Charvaka Duvvury Repr. Chichester [u.a.] Wiley 1996 XIV, 209 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Design and measurement in electronic engineering Electrostatics Integrated circuits Protection Semiconductors Semiconductors Protection Static eliminators Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Elektrostatische Entladung (DE-588)4401020-5 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 s Elektrostatische Entladung (DE-588)4401020-5 s DE-604 Duvvury, Charvaka Verfasser aut |
| spellingShingle | Amerasekera, Ajith Duvvury, Charvaka ESD in silicon integrated circuits Electrostatics Integrated circuits Protection Semiconductors Semiconductors Protection Static eliminators Integrierte Schaltung (DE-588)4027242-4 gnd Elektrostatische Entladung (DE-588)4401020-5 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4401020-5 |
| title | ESD in silicon integrated circuits |
| title_auth | ESD in silicon integrated circuits |
| title_exact_search | ESD in silicon integrated circuits |
| title_full | ESD in silicon integrated circuits Ajith Amerasekera ; Charvaka Duvvury |
| title_fullStr | ESD in silicon integrated circuits Ajith Amerasekera ; Charvaka Duvvury |
| title_full_unstemmed | ESD in silicon integrated circuits Ajith Amerasekera ; Charvaka Duvvury |
| title_short | ESD in silicon integrated circuits |
| title_sort | esd in silicon integrated circuits |
| topic | Electrostatics Integrated circuits Protection Semiconductors Semiconductors Protection Static eliminators Integrierte Schaltung (DE-588)4027242-4 gnd Elektrostatische Entladung (DE-588)4401020-5 gnd |
| topic_facet | Electrostatics Integrated circuits Protection Semiconductors Semiconductors Protection Static eliminators Integrierte Schaltung Elektrostatische Entladung |
| work_keys_str_mv | AT amerasekeraajith esdinsiliconintegratedcircuits AT duvvurycharvaka esdinsiliconintegratedcircuits |