Delta-sigma data converters: theory, design, and simulation
Gespeichert in:
| Format: | Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
New York, NY
IEEE Press
1997
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXIII, 476 S. graph. Darst. |
| ISBN: | 0780310454 |
Internformat
MARC
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Datensatz im Suchindex
| _version_ | 1804125708392333312 |
|---|---|
| adam_text | Delta-Sigma
Data Converters
Theory, Design,
and Simulation
Edited by
Steven R Norsworthy
Motorola
Richard Schreier
Oregon State University
Gabor C Temes
Oregon State University
IEEE
PRESS
IEEE Circuits amp; Systems Society, Sponsor
The Institute of Electrical and Electronics Engineers, Inc , New York
Contents
Preface xv
Introduction xvii
Chapter 1 An Overview of Basic Concepts 1
J C Candy
1 1 Introduction 1
1 2 Digital Modulation 3
121 Quantization 3
122 Delta-Sigma Modulation 5
1221 First-Order Feedback Quantizer 5
1222 Modulation Noise in Busy Signals 7
1223 Pattern Noise from AX Modulation with dc Inputs 8
1224 Dead Zones in AX Modulation 10
1225 Influence of Circuit Parameters on AX Modulation 11
123 High-Order Modulation 14
1231 Predicting In-Band Values of Quantization Error 14
1232 Noise in High-Order AX Modulation 14
1233 Dynamic Range of the Modulators 16
1234 Influence of Circuit Parameters on Second-Order Modulators 19
1235 Limit Cycles in Third-Order AX Modulators 20
1236 Noise Shaping Using Filters with Nonmonotonic Transfer Functions 22
124 Some Alternative Modulator Structures 23
1241 Error Feedback 23
1242 Cascaded Modulators 24
1243 Delta Modulation 26
v
VI Contents
Decimating the Modulated Signal 28
131 Multistage Decimation 28
132 Design of the First-Stage Decimator 29
133 Implementing sine Decimators 32
134 The Low-Pass Filter 35
Oversampling D/A Converters 36
141 Demodulating Signals at Elevated Word Rates 36
142 Interpolating with sinc^-Shaped Filter Functions 37
143 Demodulator Stage 38
1431 Quantizing the Digital Signal 38
1432 Quantization with Error Feedback 38
1433 Cascaded Demodulators 40
1434 Circuit Design for AX Demodulation 40
Conclusion 41
References 41
Chapter 2 Quantization Noise in AI A/D Converters 44
Robert M Gray
2 1 Introduction 44
2 2 Uniform Quantization 45
2 3 Additive White-Noise Approximation 46
2 4 Characteristic Function Method 53
2 5 Pulse Code Modulation Quantization Noise 55
2 6 Dithered PCM 58
2 7 Single-Loop AI Modulation 59
2 8 Two-Stage (Cascade or MASH) AI Modulation 64
2 9 Second-Order AI Modulation 66
2 10 Some Extensions 68
2 10 1 Dithered Single-Loop AX Modulation 68
2 10 2 Multistage and Higher Order AX Modulation 68
2 10 3 Leaky Integrating AX Modulation 69
2 10 4 Multibit Quantizer, Single-Bit Feedback 69
2 10 5 Related Work 69
2 11 Conclusion 70
Acknowledgments 70
References 70
Chapter 3 Quantization Errors and Dithering in AI Modulators 75
Steven R Norsworthy
3 1 Introduction 75
311 Problems with Empirically Based Reports on AX Modulators 77
312 Steps Taken to Ensure Accuracy of Results 77
3 2 Basic Structures and Terminology 78
Contents vii
3 3 Observability of Periodic Sequences 80
3 4 Tones in Single-Stage AE Modulators 84
341 Second-Order Modulator 85
342 Third-Order Modulator 88
343 Fifth-Order Modulator 92
344 Baseband Demodulation of Tones Near f/2 95
345 Higher-Order and Multibit Single-Stage Modulators 97
3 5 Tones in Multistage AE Modulators 98
3 6 Tones in AE Converter Hardware 100
361 Third-Order Digital Modulator Test 101
362 Fifth-Order Digital Modulator Test 102
363 Multistage Modulator Test 104
3 7 Dither in PCM Quantizers 104
371 Nonsubtractive Dither 104
372 Subtractive Dither 105
3 8 Dither Topologies for AE Modulators 107
381 Dither Topologies for Single-Stage Modulators 107
382 Dither Topologies for Multistage Modulators 109
3 9 Empirical Studies of Noise-Shaped Dithering 112
391 Second-Order Modulator 112
392 Third-Order Modulator 116
393 Fifth-Order Modulator 118
394 Effect of Dither on Tones Near f/2 119
395 Multistage Modulators 120
3 10 Dither Generation 121
3 11 Dither in A/D Modulators 121
3 11 1 Single-Stage A/D Modulator Example 121
3 11 2 Multistage A/D Modulators 121
3 12 Subtractive Noise-Shaped Dithering 123
3 13 Dynamic Noise-Shaped Dithering 124
3 13 1 Theory of Dynamic Dither 124
3 13 2 Implementation Considerations of Dynamic Dither 127
3 14 Dithered Multibit Noise-Shaping Coders 130
3 14 1 Stability Test with Dither 130
3 15 Chaos versus Noise-Shaped Dither 131
3 16 Other Techniques 134
3 17 Conclusion 135
References 136
Chapter 4 Stability Theory for AE Modulators 141
Robert W Adams and Richard Schreier
4 1 Introduction 141
4 2 Linear Analysis 142
421 The Linear Model 142
422 Root Locus of a High-Order Modulator 144
423 Describing Function Method 145
viii Contents
4 3 First-and Second-Order Modulators 147
431 First-Order Modulator 148
432 Second-Order Modulator 149
4 4 Practical Design Methodology 152
441 Cookbook Design Procedure 152
442 SNR Limits 153
443 Sixth-Order NTF 154
444 Design Trade-Offs 156
4 5 Continuous-Time Design 158
4 6 Nonlinear Stabilization Techniques 162
4 7 Conclusion 163
Acknowledgments 163
References 163
Chapter5 The Design of High-Order Single-Bit AX ADCs 165
Robert W Adams
5 1 Introduction 165
5 2 Motivation for Using High-Order Single-Bit Loops 166
5 3 Design Choices: SC or Active-RC? 167
5 4 Stability 170
541 Stability and the Uncontrolled Input Signal:
A Practical Guide to Safe Operation 170
542 Transient Input Signals and Stability:
The Case for Mild Prefiltering 170
5 5 Choices for the NTF 172
551 rrth-Order Pure Differentiation 172
552 Butterworth High-Pass Response 173
553 Complex Zeros on the Unit Circle (Inverse Chebyshev) 174
5 6 Comparison of Loop Topologies 174
561 Chain of Integrators with Weighted Feedforward Summation 176
562 Chain of Integrators with Feedforward Summation and Local
Resonator Feedbacks 177
563 Chain of Integrators with Distributed Feedback 178
564 Chain of Integrators with Distributed Feedback and Distributed
Feedforward Inputs 179
565 Error Feedback Only 180
5 7 Nonlinear Global Stabilization Techniques 183
5 8 Practical Measures for Preventing Idle Tones 185
5 9 Practical Implementation of a Stereo 18-Bit AX ADC 1C 186
591 Noise-Shaping Modulator 1C 186
592 Switched-Capacitor Loop Filter Design 186
593 Circuit Noise Considerations 189
594 Stabilization Using Integrator Reset 190
595 Op-Amp Design 190
596 Results and Comments 191
References 192
Contents ix
Chapter 6 The Design of Cascaded AX ADCs 193
Mike Rebeschini
6 1 Introduction 193
6 2 System Design 195
621 Comparison of Single-Loop and Cascaded Designs 195
6211 Single-Loop Designs 195
6212 Cascaded Designs 196
622 Analytical Linearized Modeling 196
623 Software Simulations 197
6 3 Analysis of Specific Cascaded Architectures 199
631 Third-Order (1-1-1) Modulator 199
632 Third-Order (2-1) Modulator 203
6 4 Circuit Topologies for Third-Order (1-1-1) Cascade 204
641 Autozeroed Integrator 204
642 First Modulator of Third-Order (1-1-1) Cascade 206
643 Second and Third Modulators of Third-Order (1-1-1) Cascade 207
6 5 Sources of Error for the Third-Order (1-1-1) Cascade 209
6 6 Experimental Results for the Third-Order (1-1-1) Cascade 211
6 7 Continuous-Time Cascaded AX Modulators 213
6 8 Conclusion 217
References 218
Chapter 7 High-Speed Cascaded AX ADCs 219
Brian Brandt
7 1 Introduction 219
7 2 AX Modulation at Low Oversampling Ratios 220
73A Cascaded Multibit AX Modulator 222
731 Interstage Coupling 225
7 4 Implementation of the Cascaded Multibit Modulator 229
741 Gain Error 230
742 Incomplete Settling 232
743 Integrator Leakage 232
7 5 Design of the Cascaded Multibit Modulator 233
7 6 Experimental Results 239
7 7 Summary 242
References 242
Chapter 8 Delta-Sigma ADCs with Multibit Internal Converters 244
Richard L Carley, Richard Schreier, and Gabor C Temes
8 1 Introduction 244
8 2 Multibit Noise-Shaping Modulator Architectures 245
8 3 DAC Architectures for Improved Linearity 247
Contents
831 Internal DAC Topology 247
832 Element-Trimming Approaches 249
8321 One-Time Trimming Methods 249
8322 Repeated Trimming Methods 251
8323 Other Element-Matching Methods 251
833 Dynamic Element Matching 251
8331 Dynamic Element Randomization 253
8332 Dynamic Element Rotation—Barrel Shifter 256
8333 Individual Level Averaging 259
8334 Noise-Shaped Element Usage 260
8 4 Digital Correction Techniques 264
841 AX ADC Architectures with Error-Storing Random-Access Memory 264
842 The Calibration of the Digitally Corrected AI ADC 265
843 An Improved Digital Correction System 267
844 Cascade AI ADC Systems Using Digital Correction 269
845 Digitally Corrected AI ADC with Companding Quantizer 270
8 5 Dual-Quantizer ADC Architectures 273
851 The Leslie-Singh Architecture 273
852 Dual-Quantization Cascade ADC Architectures 275
853 Dual-Feedback Single-Path ADC Architecture 276
8 6 Conclusion 277
References 278
Chapter 9 The Design of Bandpass AX ADCs 282
Stephen Jantzi, Richard Schreier, and Martin Snelgrove
9 1 Introduction 282
9 2 Bandpass AI Transfer Function Design 284
921 The Linear Model 285
922 Band Location 285
923 Low-Pass Prototype Method 286
924 Design by Generalized Filter Approximator 287
9241 The Design of H(z) 287
9242 The Design of G(z) 288
9243 An Example Modulator 288
925 Modulator Performance 289
9251 Linear Model Predictions 289
9252 Simulations 290
9253 SNR versus Modulator Order and Oversampling Ratio 291
9 3 Bandpass AI Modulator Design 292
931 Standard Switched-Capacitor Design 292
932 Switched-Capacitor «-Path Design 294
933 Practical Considerations in Discrete-Time Systems 296
9331 Capacitor and 1//Noise 296
9332 Op-amp Speed 297
9333 Sample-and-Hold Circuits 297
934 Continuous-Time Design 297
9 4 Decimation for Bandpass Modulators 300
Contents xi
9 5 Experimental Results 301
951 Reported Implementations of Bandpass AX Modulators 301
9511 September 1990 301
9512 September 1991 301
9513 May 1992 302
9514 June 1992 302
9515 February 1993 303
9516 May 1994 304
952 Performance Summary 304
953 Comments on Bandpass AX Modulator Performance 304
9 6 The Future of Bandpass AX Modulation 305
961 High-Frequency Converters 305
962 Bandpass AX DACs 306
9 7 Conclusion 306
References 306
Chapter 10 Architectures for AX DACs 309
Gabor C Temes, Shaofeng Shu, and Richard Schreier
10 1 Introduction 309
10 2 Architectures for the Noise-Shaping Loop 311
10 2 1 Delta-Sigma Loop 311
10 2 2 Error Feedback Structure 313
10 2 3 Cascade Structure 315
10 2 4 Multibit Quantizer Loops 316
10 3 Design Example 1: A Fifth-Order Single-Bit Noise-Shaping Loop 321
10 3 1 The Noise Transfer Function 321
10 3 2 The Modulator Structure 322
10 4 Design Example 2: A Third-Order (2+1) Multibit Cascade
Noise-Shaping Loop 324
10 5 Conclusion 331
References 332
Chapter 11 Analog Circuit Design for AX ADCs 333
Brian Brandt, Paul F Ferguson, and Mike Rebeschini
11 1 Introduction 333
11 2 Architectural Considerations 334
11 3 Building Blocks 336
11 3 1 Input Integrator 336
11 3 2 Specifications 337
11 3 3 Fully Differential SC Integrator 337
11 3 4 Op-Amp 343
11 4 Circuit Nonidealities 348
11 4 1 Effects of Component Nonidealities on the Integrator Performance 348
11 4 2 Nonlinear Effects 350
11 4 3 Intrinsic Noise 353
Contentsxii
11 5 Modulator Component Design Considerations 356
11 5 1 The Feedback DAC 356
11 511 Reference Nonidealities 356
11 512 Charge-Taking Nonidealities 357
11 513 Charge-Delivery Nonidealities 358
11 5 2 The Comparator 360
11 5 3 The Clock Generation Circuitry 361
11 6 System-Level Considerations 361
11 6 1 Dynamic Range Considerations 361
11 6 2 Clock Jitter 363
11 6 3 Input Impedance 363
11 7 Layout Considerations 365
11 7 1 Signal Paths 365
11 7 2 Busses 365
11 7 3 RF Coupling 366
11 7 4 Interlacing to the ADC 367
11 8 Design Examples 369
11 8 1 Second-Order Single-Stage AI Modulator 369
11 8 2 Second-Order Cascaded Modulator (1-1) 373
11 9 Conclusion 378
References 378
Chapter 12 Analog Circuit Design for AI DACs 380
Mike Rebeschini and Paul F Ferguson, Jr
12 1 Introduction 380
12 2 Building Blocks 381
12 2 1 The Low-Resolution Input DAC 382
12 2 2 Voltage References 384
12 2 3 Reconstruction Filter 386
12 231 Specifications 386
12 232 Switched-Capacitor Reconstruction Using Biquads 387
12 233 Noise-Shaping Filter 389
12 234 Analog Decimation Filters for AI DACs 390
12 235 Effect of Nonideal Integrator Transfer Function 394
12 2 4 Discrete-Time/Continuous-Time Interface 395
12 241 Final Discrete-Time Stage 395
12 242 Continuous-Time Reconstruction Filter 396
12 2 5 Other Nonideal Effects 397
12 251 Intrinsic Noise 397
12 252 Dynamic Range Considerations 398
12 3 Layout Considerations 398
12 3 1 Differences from the ADC 398
12 3 2 Layout Influences on the Architecture 399
12 4 Design Examples 399
12 41A One-Bit High-Order AI DAC 399
12 42A MASH DAC 403
12 4 3 Recent Developments 404
References 404
Contents xiii
Chapter 13 Decimation and Interpolation for AS Conversion 406
Steven R Norsworthy and Ronald E Crochiere
13 1 Introduction 406
13 2 Scope of Design Trade-Offs and Alternatives 408
13 3 Basic Principles of Sampling Rate Conversion—Algorithm Issues 408
13 3 1 Decimation by M 410
13 3 2 Interpolation by S 411
13 3 3 Duality 411
13 3 4 Fractional Rate Changing 413
13 4 Multistage Conversion 413
13 5 Filter Design Considerations 416
13 5 1 sine* Filters 416
13 5 2 Half-Band Filters 418
13 5 3 Ternary-Encoded FIR Filters 419
13 5 4 Combining sine* Filters with FIR and HR Filters 420
13 5 5 Minimum-Phase FIR Filters 421
13 5 6 Compensation Techniques 421
13 6 Digital Filter Structures 422
13 6 1 Direct-Form and Transpose Direct-Form Decimators and Interpolators
13 6 2 Polyphase Architectures for Decimators and Interpolators 426
13 6 3 Multistage Architectures 429
13 7 Hardware Implementation—Architectural Issues 432
13 7 1 Historical Background 432
13 7 2 Architectural Features and Styles 432
13 7 3 Arithmetic Processing Issues 433
13 731 Bit-Serial and Digit-Serial Arithmetic 433
13 732 Parallel Multiplication 435
13 733 Combined Bit-Serial and Bit-Parallel Architectures 435
13 734 Single-Multiplier Architectures 436
13 7 4 DSP and Programmable Implementations 438
13 741 Multirate Filtering Efficiency on DSPs 440
13 742 Multistage Implementation Including sine* Filters 441
13 743 Data Transfers and Buffering Between the Stages 441
13 7 5 Mixed Analog and Digital Implementations 443
13 8 Conclusion 443
Acknowledgments 444
References 444
Chapter 14 CAD for the Analysis and Design of AI Converters 447
Christopher Wolff, John G Kenney, and L Richard Carley
14 1 Introduction 447
14 2 Multibit Converter Design 447
14 2 1 Accumulation of Quantization Error 448
14 2 2 Formulation and Solution of the Optimization Problem 449
xiv Contents
14 221 Quantization Noise 450
14 222 Constraints 450
14 223 Representation of Closed-Loop Poles for the Optimizer 451
14 2 3 Example Results 451
14 3 Simulation Based on Difference Equations 452
14 4 Simulation Based on the Quantizer Transfer Function 453
14 4 1 Statistical Average Quantizer Transfer Function 453
14 4 2 Distortion 455
14 5 Simulation Approaches 458
14 5 1 Overview 458
14 5 2 Model Comparison 459
14 5 3 Efficient Macromodel Simulation 460
14 6 Conclusion 463
References 464
For Further Reading 466
Index 469
About the Editors 475
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| id | DE-604.BV011210962 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:05:51Z |
| institution | BVB |
| isbn | 0780310454 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007520169 |
| oclc_num | 34475103 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-92 DE-29T DE-861 DE-898 DE-BY-UBR DE-858 DE-634 |
| owner_facet | DE-91 DE-BY-TUM DE-92 DE-29T DE-861 DE-898 DE-BY-UBR DE-858 DE-634 |
| physical | XXIII, 476 S. graph. Darst. |
| publishDate | 1997 |
| publishDateSearch | 1997 |
| publishDateSort | 1997 |
| publisher | IEEE Press |
| record_format | marc |
| spelling | Delta-sigma data converters theory, design, and simulation ed. by Steven R. Norsworthy ... Delta sigma New York, NY IEEE Press 1997 XXIII, 476 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Analog-to-digital converters Digital-to-analog converters Modulators (Electronics) Design Modulation (DE-588)4039849-3 gnd rswk-swf Analog-Digital-Umsetzer (DE-588)4128359-4 gnd rswk-swf Digital-Analog-Umsetzer (DE-588)4128360-0 gnd rswk-swf Analog-Digital-Umsetzer (DE-588)4128359-4 s DE-604 Modulation (DE-588)4039849-3 s 1\p DE-604 Digital-Analog-Umsetzer (DE-588)4128360-0 s 2\p DE-604 Norsworthy, Steven R. Sonstige oth HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007520169&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Delta-sigma data converters theory, design, and simulation Analog-to-digital converters Digital-to-analog converters Modulators (Electronics) Design Modulation (DE-588)4039849-3 gnd Analog-Digital-Umsetzer (DE-588)4128359-4 gnd Digital-Analog-Umsetzer (DE-588)4128360-0 gnd |
| subject_GND | (DE-588)4039849-3 (DE-588)4128359-4 (DE-588)4128360-0 |
| title | Delta-sigma data converters theory, design, and simulation |
| title_alt | Delta sigma |
| title_auth | Delta-sigma data converters theory, design, and simulation |
| title_exact_search | Delta-sigma data converters theory, design, and simulation |
| title_full | Delta-sigma data converters theory, design, and simulation ed. by Steven R. Norsworthy ... |
| title_fullStr | Delta-sigma data converters theory, design, and simulation ed. by Steven R. Norsworthy ... |
| title_full_unstemmed | Delta-sigma data converters theory, design, and simulation ed. by Steven R. Norsworthy ... |
| title_short | Delta-sigma data converters |
| title_sort | delta sigma data converters theory design and simulation |
| title_sub | theory, design, and simulation |
| topic | Analog-to-digital converters Digital-to-analog converters Modulators (Electronics) Design Modulation (DE-588)4039849-3 gnd Analog-Digital-Umsetzer (DE-588)4128359-4 gnd Digital-Analog-Umsetzer (DE-588)4128360-0 gnd |
| topic_facet | Analog-to-digital converters Digital-to-analog converters Modulators (Electronics) Design Modulation Analog-Digital-Umsetzer Digital-Analog-Umsetzer |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007520169&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT norsworthystevenr deltasigmadataconverterstheorydesignandsimulation AT norsworthystevenr deltasigma |