Behavioral synthesis: digital system design using the synopsys behavioral compiler
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Upper Saddle River, NJ
Prentice Hall
1996
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | IX, 231 S. graph. Darst. Diskette (9 cm) |
| ISBN: | 0135692520 |
Internformat
MARC
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| 100 | 1 | |a Knapp, David W. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Behavioral synthesis |b digital system design using the synopsys behavioral compiler |c David W. Knapp |
| 264 | 1 | |a Upper Saddle River, NJ |b Prentice Hall |c 1996 | |
| 300 | |a IX, 231 S. |b graph. Darst. |e Diskette (9 cm) | ||
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| 650 | 4 | |a Circuits électroniques - Calcul - Informatique | |
| 650 | 4 | |a Compilateurs (Logiciels) | |
| 650 | 4 | |a Conception assistée par ordinateur | |
| 650 | 4 | |a Langages de description de matériel informatique | |
| 650 | 7 | |a Réseaux électriques (circuits) |2 ram | |
| 650 | 4 | |a Systèmes, Conception de - Informatique | |
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Compilers (Computer programs) | |
| 650 | 4 | |a Computer hardware description languages | |
| 650 | 4 | |a Computer-aided design | |
| 650 | 4 | |a Electronic circuit design |x Data processing | |
| 650 | 4 | |a System design |x Data processing | |
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| 999 | |a oai:aleph.bib-bvb.de:BVB01-007512922 | ||
Datensatz im Suchindex
| _version_ | 1804125698037645312 |
|---|---|
| adam_text | BEHAVIORAL
SYNTHESIS
Digital System Design Using the
Synopsys® Behavioral Compiler™
David W Knapp
For book and bookstore information
http://www prenhall com
sdM Prentice Hall PTR
Upper Saddle River, New Jersey 07458
Contents
Preface v
X Introduction X
1 1 Design Flow 1
1 2 Simulation and Verification 5
1 3 RTL and Behavioral Design 6
1 4 Behavioral Compiler Design Flow 10
Behavioral Compiler 14
2 1 Inputs 14
2 2 Behavioral Compilation: Internals 17
221 Representations 17
222 Scheduling 22
223 Allocation 25
224 Netlisting 27
225 Control FSM 27
226 Invoking the scheduler 29
2 3 BC Outputs 30
HDL Descriptions 32
3 1 The Design 34
3 2 Behavioral Processes 34
3 3 Clock and Reset 36
3 4 I/O Operations 39
3 5 Flow of Control 41
3 6 Memory Inference 47
3 7 Synthetic Components 52
i
ii Contents
3-8 Preserved Functions 53
3 9 Pipelined Components 54
3 10 Random Logic 55
4 I/O modes 57
4 1 Cycle-Fixed Mode 60
411 Rules for Fixed Mode 62
4 2 Superstate-Fixed Mode 65
421 Rules for superstate mode 66
4 3 Free-Floating Mode 68
4 4 Control Unit Registers 71
5 Explicit Directives and Constraints 74
5 1 Labeling 74
5 2 Scheduling Constraints 76
5 3 Options 77
5 4 Test Benches; Simulation 80
6 Reports 83
6 1 Timing report 83
6 2 Reservation tables 86
621 Operation Reports 86
622 Variable Storage Reports 87
6 3 State Machine Reports 90
6 4 Error messages 91
7 FIR filter 99
7 1 Initial Design 99
7 2 Synthesis 105
7 3 Simulation 114
7 4 Decreasing cost 118
8 IIR filter: handshaking I/O protocol 125
8 1 Initial Design 125
8 2 Simulation 132
8 3 Synthesis 137
8 4 Speeding up the Clock 147
9 The Inverse Discrete Cosine IY ansform: C to HDD
158
CONTENTS
iii
9 1 Initial C Code 158
9 2 Translation into HDL 160
9 3 Simulation 165
10 The Data Encryption Standard: Random Logic 184
10 1 General Description 184
10 2 HDL Description 185
10 3 Synthesis 191
10 4 Use of DesignWare 192
11 Packet router 195
A Constructing DesignWare 202
A l Combinational DesignWare 202
A 2 Sequential DesignWare 209
B Synthesizable Subsets 221
B l VHDL Subset 221
Bll VHDL constructs that are only partially supported 223
Bl2 VHDL constructs that are ignored by synthesis 223
Bl3 Unsupported VHDL Constructs 223
Bl4 Special attributes for synthesis in VHDL 224
B 2 Verilog Subset 224
B21 Fully supported Verilog constructs 224
B22 Verilog constructs that are not fully supported 225
|
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| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
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| id | DE-604.BV011201789 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:05:41Z |
| institution | BVB |
| isbn | 0135692520 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007512922 |
| oclc_num | 35110545 |
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| owner | DE-91 DE-BY-TUM |
| owner_facet | DE-91 DE-BY-TUM |
| physical | IX, 231 S. graph. Darst. Diskette (9 cm) |
| publishDate | 1996 |
| publishDateSearch | 1996 |
| publishDateSort | 1996 |
| publisher | Prentice Hall |
| record_format | marc |
| spelling | Knapp, David W. Verfasser aut Behavioral synthesis digital system design using the synopsys behavioral compiler David W. Knapp Upper Saddle River, NJ Prentice Hall 1996 IX, 231 S. graph. Darst. Diskette (9 cm) txt rdacontent n rdamedia nc rdacarrier Circuits électroniques - Calcul - Informatique Compilateurs (Logiciels) Conception assistée par ordinateur Langages de description de matériel informatique Réseaux électriques (circuits) ram Systèmes, Conception de - Informatique Datenverarbeitung Compilers (Computer programs) Computer hardware description languages Computer-aided design Electronic circuit design Data processing System design Data processing HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007512922&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Knapp, David W. Behavioral synthesis digital system design using the synopsys behavioral compiler Circuits électroniques - Calcul - Informatique Compilateurs (Logiciels) Conception assistée par ordinateur Langages de description de matériel informatique Réseaux électriques (circuits) ram Systèmes, Conception de - Informatique Datenverarbeitung Compilers (Computer programs) Computer hardware description languages Computer-aided design Electronic circuit design Data processing System design Data processing |
| title | Behavioral synthesis digital system design using the synopsys behavioral compiler |
| title_auth | Behavioral synthesis digital system design using the synopsys behavioral compiler |
| title_exact_search | Behavioral synthesis digital system design using the synopsys behavioral compiler |
| title_full | Behavioral synthesis digital system design using the synopsys behavioral compiler David W. Knapp |
| title_fullStr | Behavioral synthesis digital system design using the synopsys behavioral compiler David W. Knapp |
| title_full_unstemmed | Behavioral synthesis digital system design using the synopsys behavioral compiler David W. Knapp |
| title_short | Behavioral synthesis |
| title_sort | behavioral synthesis digital system design using the synopsys behavioral compiler |
| title_sub | digital system design using the synopsys behavioral compiler |
| topic | Circuits électroniques - Calcul - Informatique Compilateurs (Logiciels) Conception assistée par ordinateur Langages de description de matériel informatique Réseaux électriques (circuits) ram Systèmes, Conception de - Informatique Datenverarbeitung Compilers (Computer programs) Computer hardware description languages Computer-aided design Electronic circuit design Data processing System design Data processing |
| topic_facet | Circuits électroniques - Calcul - Informatique Compilateurs (Logiciels) Conception assistée par ordinateur Langages de description de matériel informatique Réseaux électriques (circuits) Systèmes, Conception de - Informatique Datenverarbeitung Compilers (Computer programs) Computer hardware description languages Computer-aided design Electronic circuit design Data processing System design Data processing |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007512922&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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