Proceedings 1996: Las Vegas Convention Center, Las Vegas, NV. ; June 3 - 7, 1996
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| Format: | Tagungsbericht Buch |
| Sprache: | English |
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Piscataway, NJ
IEEE
1996
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| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXX, 839 S. Ill., graph. Darst. |
| ISBN: | 0780333640 0780332946 0780332954 0897917790 |
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| 245 | 1 | 0 | |a Proceedings 1996 |b Las Vegas Convention Center, Las Vegas, NV. ; June 3 - 7, 1996 |c 33rd Design Automation Conference |
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Table of Contents
General Chair’s Welcome
Executive Committee
iii
Technical Program Committee vi
1996 Best Paper Award Viti
ACM Awards/Fellows and IEEE Fellows Viti
34th Call for Papers ix
ACSEE Undergraduate Scholarships x
Design Automation Conference Scholarship Awards x
Reviewers xii
Opening Keynote Address—Arati Prabhakar xv
Wednesday Keynote Address—James Clark xvi
Thursday Keynote Address—Eric Schmidt xvii
Session 1
Executive Forum
Panel: The EDA Year in Review: CEO’s, The Press, and Users
Chair: John Cooley
Organizer: John Cooley
Panelists: Joe Costello, Aart de Geus, Richard Goering, Alain Hanover,
Wally Rhines, Gary Smith 1
Session 2
High Speed Interconnect
Chair: Gary Smith
Organizer: S Boose
2 1 Package and Interconnect Modeling of the HFA3624, a 2 4GHz RF to IF Converter
Mattan Kamon, Steve S Majors 2
Panel: PCB Synthesis—Is the Technology
Ready for High Speed Design?
Panelists: Robert Gonzales, Mark Leonard, Fred Saal, John Schoenfeld,
Jonathan Weis, Mike White 8
Session 3
Power Analysis
Chair: Bob Frye
Organizers: S Nance, N Weste
31 HEAT: Hierarchical Energy Analysis Tool
Janardhan H Satyanarayana, Keshab K Parhi I
3 2 Opportunities and Obstacles in Low-Power System-Level CAD
Andrew Wolfe 15
3 3 POSE: Power Optimization and Synthesis Environment
Sasan Iman, Massoud Pedram 21
3 4 Early Power Exploration—A World Wide Web Application
David Lidsky, Jan M Rabaey 27
xviii
41
Session 4
Current Directions in High Level Synthesis
Chair: Hiroto Yasuura
Organizers: R Walker, K Wakabayashi
Tutorial: Behavioral Synthesis
Raul Camposano eneneneeeenen 33
A Register File and Scheduling Model for Application Specific Processor Synthesis
E Ercanli, C Papachristou 35
Optimized Code Generation of Multiplication-Free Linear Transforms
Mahesh Mehendale, G Venkatesh, S D Sherlekar csscsccssessssstccssnessssestecssssstecetseassesecess 41
Concurrent Analysis Techniques for Data Path Timing Optimization
Chuck Monahan, Forrest Brewer 47
HDL Optimization Using Timed Decision Tables
Jian Li, Rajesh K Gupta 51
Session 5
Analysis and Synthesis of Asynchronous Circuits
Chair: Peter Beerel
Organizers: L Lavagno, B Lin
Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems
Eric Verlind, Gjalt de Jong, Bill Lin 55
Verification of Asynchronous Circuits Using Time Petri Net Unfolding
Alexei Semenov, Alexandre Yakovlev 59
Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev,
Luciano Lavagno, Alex Yakovlev 63
A Technique for Synthesizing Distributed Burst-Mode Circuits
Prabhakar Kudva, Ganesh Gopalakrishnan, Hans Jacobson enesenerssnssnunsanneneennarsennennnennn 67
Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic
Michael Theobald, Steven M Nowick, Tao Wu 71
Synthesis of Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-
Input Changes
Prabhakar Kudva, Ganesh Gopalakrishnan, Hans Jacobson, Steven M Nowick 00+ 77
Session 6
New Frontiers in Partitioning
Chair: D F Wong
Organizers: A Domic, A B Kahng
Tutorial: Partitioning of VLSI Circuits and Systems
Frank M Joh 83
New Spectral Linear Placement and Clustering Approach
Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng ussersenseisenseesssntonnesenuenenenene 88
Characterization and Parameterized Random Generation of Digital Circuits
Michael Hutton, J P Grossman, Jonathan Rose, Derek Corneil unussenssessesssosssneenenne 94
A Probability-Based Approach to VLSI Circuit Partitioning
Shantanu Dutt, Wenyong Deng 100
xix
Session 7
Trends in Verification
Chair: James Rowson
Organizers: N Collins, R Goering
TA Tutorial: Verification of Electronic Systems
Alberto L Sangiovanni-Vincentelli, Patrick C McGeer, Alexander Saldanha nn 106
Panel: Hot New Trends in Verification
Panelists: Anant Agarwal, Willis Hendley, Isadore Katz,
Don Mclnnis, Patrick Scaglia, Alex Silbey 112
Session 8
Specialized Design Techniques for Speed and Power
Chair: Scott Nance
Organizers: D Stark, B Frye
8 1 Design Considerations and Tools for Low-voltage Digital System Design
Anantha Chandrakasan, Isabel Yang, Carlin Vieri, Dimitri Antoniadis 2 000-0000ee 113
8 2 VAMP: A VHDL Based Concept for Accurate Modeling and Post Layout Timing
Simulation of Electronic Systems
Bernhard Wunder, Gunther Lehmann, Klaus D Milller-Glaser ccssssscsssssssseerseneenonne 119
83 A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU
Design Using Circuit Simulation
Madhav P Desai, Y T Yen 125
Session 9
Test and Fault Tolerance in High Level Synthesis
Chair: C Papachristou
Organizers: K Wakabayashi, R Camposano
9 1 Tutorial: High-Level Synthesis for Testability: A Survey and Perspective
Kenneth D Wagner, Sujit Dey 131
9 2 Introspection: A Low Overhead Binding Technique During Self-Diagnosing
Microarchitecture Synthesis
Balakrishnan Iyer, R h Karri 137
93 Lower Bounds on Test Resources for Scheduled Data Flow Graphs
Ishwar Parulkar, Sandeep K Gupta, Melvin A Breuer nessenssunesnunensnennssnnnsenenrnesenne 143
Session 10
Issues in Discrete Simulation
Chair: Jay Lawrence
Organizers: R McGeer, K Sakallah
10 1 Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation
of VLSI Systems
Antonio R W Todesco, Teresa H -Y Meng 149
10 2 Oscillation Control in Logic Simulation Using Dynamic Dominance Graphs
Peter Dahlgren 155
103 Compact Vector Generation for Accurate Power Simulation
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee 161
10 4 Improving the Efficiency of Power Simulators by Input Vector Compaction
Chi-ying Tsui, Radu Marculescu, Diana Marculescu, Massoud Pedram nnnunneone 165
11 2
Session 11
Issues in Design Environments
Chair: Michaela Guiney
Organizers: D Ku, R A Rutenbar
Efficient Communication in a Design Environment
‚Idalina Videira, Paulo Verfssimo, Helena Sarmento unensnesssensnsenesunsssenssenenseonennenennenn 169
A Description Language for Design Process Management
Peter R Sutton, Stephen W Director 175
Improved Tool and Data Selection in Task Management
John W Hagerman, Stephen W Director 181
Application of a Markov Model to the Measurement, Simulation, and Diagnosis of an
Iterative Design Process
Eric W Johnson, Luis A Castillo, Jay B Brockman wo ccsccsssscsccscereetsesssennestesetseenneceneaceeaees 185
Session 12
Panel: Gearing Up for the Technology Explosion
Chair: Gary Smith
Organizer: M Kenefick
Panelists: Walt Davis, Glenn House, Kurt Keutzer, Jim Pena, Craig Peterson,
Lawrence Rubin, Jim Solomon 189
Session 13
Tutorial: The SPICE FET Models: Pitfalls and Prospects
(Are You An Educated Model Consumer?)
Chair: Daniel Foty
Organizer: J Cooley
Presenter: Daniel Foty 190
Session 14
Combinational Logic Synthesis I
Chair: Gary D Hachtel
Organizers: S Malik, R McGeer
Tutorial: Design of a Logic Synthesis System
Richard Rudell 191
On Solving Covering Problems
Olivier Coudert 197
Session 15
Pattern Generation for Test and Diagnosis
Chair: Janusz Rajski
Organizers: S Kundu, Y Zorian
A New Complete Diagnosis Patterns for Wiring Interconnects
Sungju Park 203
A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuits
Chih-Ang Chen, Sandeep K Gupta 209
On Static Compaction of Test Sequences for Synchronous Sequential Circuits
Irith Pomeranz, Sudhakar M Reddy 215
xxi
16 1
Session 16
CAD for Analog and Mixed Signal ICs
Chair: James Spoto
Organizers: R A Rutenbar, J White
An O(n) Algorithm for Transistor Stacking with Performance Constraints
Bulent Basaran, Rob A Rutenbar :
Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design
Paolo Miliozzi, lasson Vassiliou, Edoardo Charbon, Enrico Malavasi,
Alberto L, Sangiovanni-Vincentelli
RTL Emulation: The Next Leap in System Verification
Sanjay Sawant, Paul Giordano
Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits
Carsten Borchers, Lars Hedrich, Erich Barke
Session 17
Panel: Core-Based Design for System-Level ASICs—
Whose Job Is It?
Chair: Lynn Watson
Organizer: R Goldman
Panelists: Kim Asal, Andreas Danuser, Chris King, Susan Mason,
Jim Pena, Scott Runner
Session 18
Panel: A Common Standards Roadmap
Chair: Alain Hanover
Organizer: J Smith
Panelists: Rich Goldman, Andy Graham, Randolph E Harr, Gregory W Ledenbach,
A Richard Newton, Robert Rozeboom, Tabuchi Kinya
Session 19
Combinational Logic Synthesis II
Chair: Iris Bahar
Organizers: R McGeer, S Malik
Multilevel Logic Synthesis for Arithmetic Functions
Chien-Chung Tsai, Malgorzata Marek-Sadowska
Synthesis by Spectral Translation Using Boolean Decision Diagrams
Jeffery P Hansen, Masatoshi Sekine
Delay Minimal Decomposition of Multiplexers in Technology Mapping
Shashidhar Thakur, D F Wong, Shankar Krishnamoorthy
Error Correction Based on Verification Techniques
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
Session 20
Design for Testability
Chair: Yervant Zorian
Organizers: S Kundu, J Rajski
Layout Driven Selecting and Chaining of Partial Scan Flip-Flops
Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang «nennen nenn enter 262
Test Point Insertion: Scan Paths Through Combinational Logic
Chih-chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng,
Mike Tien-Chien Lee
20 3
Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming
Huoy-Yu Liou, Ting-Ting Y Lin, Chung-Kuan Cheng neseresessenennnnonnonenennursnenanennnenenennnnne 274
Session 21
Advances in Electrical Simulation
Chair: Peter Feldmann
Organizers: J White, A T Yang
Stable and Efficient Reduction of Large, Multiport RC Networks by Pole Analysis via
Congruence Transformations
Kevin J Kerns, Andrew T Yang 280
Homotopy Techniques for Obtaining a DC Solution of Large-Scale MOS Circuits
J S Roychowdhury, R C Melville 286
Efficient AC and Noise Analysis of Two-Tone RF Circuits
Ricardo Telichevesky, Ken Kundert, Jacob White 292
Session 22
Mixed Signal Design
Chair: Stephan Ohr
Organizers: S Napper, R A Rutenbar
Tutorial: Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend
Strategies
L Richard Carley, Georges G E Gielen, Rob A Rutenbar,
Willy M C Sansen 298
Panel: Mixed Signal Designs: Are There Solutions Today?
Panelists: Ariel Cao, Georges Gielen, Felicia James, Rob A Rutenbar,
Baker P Scott, David Squires 304
Session 23
Functional Verification of Microprocessors
Chair: Rajesh Raina
Organizers: N Weste, P Duncan
Code Generation and Analysis for the Functional Verification of Microprocessors
Anoosh Hosseini, Dimitrios Mavroidis, Pavlos Konas sssnsesnensssssnensusssosuansesnsnanennnnnunnnnne 305
Innovative Verification Strategy Reduces Design Cycle Time for High-End SPARC
Processor
Val Popescu, Bill McNamara 311
Hardware Emulation for Functional Verification of K5
Gopi Ganapathy, Ram Narayan, Glenn Jorden, Denzil Fernandez, Ming Wang,
Jim Nishimura 315
Functional Verification Methodology for the PowerPC 604™ Microprocessor
James Monaco, David Holloway, Rajesh Raina 319
I’m Done Simulating: Now What? Verification Coverage Analysis and Correctness
Checking of the DECchip 21164 Alpha Microprocessor
Michael Kantrowitz, Lisa M Noack 325
Session 24
High Level Power Optimization
Chair: David Knapp
Organizers: R Camposano, R Walker
Glitch Analysis and Reduction in Register Transfer Level Power Optimization
Anand Raghunathan, Sujit Dey, Niraj K Jha 331
xxiii
24 2
An Effective Power Management Scheme for RTL Design Based on Multiple Clocks
C Papachristou, M Spinning, M Nourani 337
Power Optimization in Programmable Processors and ASIC Implementations of Linear
Systems: Transformation-based Approach
Mani Srivastava, Miodrag Potkonjak 343
Scheduling Techniques to Enable Power Management
José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar uensneeneenneneesernee een 349
Electromigration Reliability Enhancement Via Bus Activity Distribution
Aurobindo Dasgupta, R h Karri 353
Session 25
3-D Parasitic Extraction
Chair: Andrew T Yang
Organizers: J White, A Yang
A Sparse Image Method for BEM Capacitance Extraction
Byron Krauter, Yu Xia, Aykut Dengi, Lawrence T Pile ggi cscssssssssseseeesersessseereenneens 357
A Parallel Precorrected FFT Based Capacitance Extraction Program for Signal Integrity
Analysis
N R Aluru, V B Nadkarni, J White nanenunsssnssssonsossnsanensannnnnnnnssnssssensenenssasareronse 363
Multipole Accelerated Capacitance Calculation for Structures with Multiple Dielectrics
with High Permittivity Ratios
Johannes Tausch, Jacob White cccccsssscsssssessssvsscscssneessssessessectencceeassesseeusssennenenennenentetey 367
Fast Parameters Extraction of Generali Three-Dimension Interconnects Using Geometry
Independent Measured Equation of Invariance
Weikai Sun, Wayne Wei-Ming Dai, Wei Hong 371
Efficient Full-Wave Electromagnetic Analysis Via Model-Order Reduction of Fast
Integral Transforms
Joel R Phillips, Eli Chiprout, David D Ling 377
Session 26
Routing Optimization for Performance
Chair: M Marek-Sadowska
Organizers: A B Kahng, Y -L Lin
Useful-Skew Clock Routing with Gate Sizing for Low Power Design
Joe G Xi, Wayne W -M Dai 383
Sizing of Clock Distribution Networks for High Performance CPU Chips
Madhav P Desai, Radenko Cvijetic, James Jensen 389
New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and
Simultaneous Wire Sizing
John Lillis, Chung-Kuan Cheng, Ting-Ting Y Lin, Ching-Yen Ho nenne 395
Constructing Lower and Upper Bounded Delay Routing Trees Using Linear
Programming
Jaewon Oh, Iksoo Pyo, Massoud Pedr 401
Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian
Relaxation
Chung-Ping Chen, Yao-Wen Chang, D F Wong 405
Session 27
Tutorial: How to Write AWK and Perl Scripts to Enable Your EDA Tools to
Work Together
Chair: Shankar Hemmady
Organizer: J Cooley
Presenters: Robert C Hutchins, Shankar Hi Ay
Session 28
Functional Verification Techniques
Chair: Neil Weste
Organizers: B Frye, D Stark
28 1 The Automatic Generation of Functional Test Vectors for Rambus Designs
K D Jones, J P Privitera
28 2 Functional Verification Methodology of Chameleon Processor
Frangoise Casaubieilh, Anthony Mclsaac, Mike Benjamin, Mike Bartley, Francois
Pogodalla, Frédéric Rocheteau, Mohamed Belhadj, Jeremy Eggleton, Gérard Mas,
Geoff Barrett, Christian Berthet
28 3 Experience in Designing a Large-scale Multiprocessor Using Field-Programmable
Devices and Advanced CAD Tools
S Brown, N Manjikian, Z Vranesic, S Caranci, A Grbic, R Grindley, M Gusat,
K Loveless, Z Zilic, S Srbljic
Session 29
Power Estimation
Chair: Lawrence T Pileggi
Organizers: K Sakallah, P McGeer
29 1 Power Estimation of Cell-Based CMOS Circuits
Alessandro Bogliolo, Luca Benini, Bruno Ricco
29 2 A New Hybrid Methodology for Power Estimation
David Ihsin Cheng, Kwang-Ting Cheng, Deborah C Wang,
Malgorzata Marek-Sadowska
29 3 A Statistical Approach to the Estimation of Delay-Dependent Switching Activities in
CMOS Combinational Circuits
Yong Je Lim, Kyung-Im Son, Heung-Joon Park, Mani Soma nesssssesnanseneanoonenssnanennn
Session 30
Optimization of Sequential Circuits
Chair: Gary D Hachtel
Organizers: F Somenzi, B Lin
30 1 Engineering Change in a Non-Deterministic FSM Setting
Sunil P Khatri, Amit Narayan, Sriram C Krishnan, Kenneth L McMillan,
Robert K Brayton, A Sangiovanni-Vincentelli
30 2 Identifying Sequential Redundancies Without Search
Mahesh A Iyer, David E Long, Miron Abramovici
30 3 A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines
Hiroyuki Higuchi, Yusuke Matsunaga
30 4 Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques
Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino,
Donatella Sciuto
KXV
31 1
Session 31
Topics in Physical Design
Chair: Lou Scheffer
Organizers: A B Kahng, A Domic
Module Compaction in FPGA-based Regular Datapaths
ANdreGs KOCH Liv eccssecesscscscssssessssnevensnencsvaensesensssesenecesestsesenesususussaeseaestassesesqeesneeeesesatonsaneaseees 471
Network Partitioning into Tree Hierarchies
Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng nnneneeeeneensnunnen 477
Efficient Approximation Algorithms for Floorplan Area Minimization
Danny Z Chen, Xiaobo (Sharon) Hu 483
Optimal Wire-Sizing Formula Under the Elmore Delay Model
Chung-Ping Chen, Yao-Ping Chen, D F Wong unneesssnnnorosonnnnenemtesnnnnenennnennennaennean 487
Session 32
Consumer Product Design
Chair: Takayasu Sakurai
Organizers: T Sakurai, S Trimberger
VLSI Design and System Level Verification for the Mini-Disc
Tetsuya Fujimoto, Takashi Kambe 491
Design Methodologies for Consumer-Use Video Signal Processing LSIs
Hisakazu Edamatsu, Satoshi Ikawa, Katsuya Hasegawa nnenenesensenenenesnnenenernenneen en 497
Design Methodology for Analog High Frequency ICs
Yasunori Miyahara, Yoshitomo Oumi, Seijiro Moriyama nesesnsunenenesenneeennenennnennen 503
Session 33
Tutorial: Issues and Answers in CAD Tool Interoperability
Chair: Mike Murray
Organizer: M Murray
Presenters: Mike Murray, Uwe B Meding, Bill Berg, Yatin Trivedi, Bill McCaffrey,
Ted Vucurevich 309
Session 34
Hardware-Software Co-Design
Chair: Frank Vahid
Organizers: R Gupta, L Lavagno
Tutorial: The Design of Mixed Hardware/Software Systems
Jay K Adams, Donald E Thomas 515
Constructing Application-Specific Heterogeneous Embedded Architectures from
Custom HW/SW Applications
Steven Vercauteren, Bill Lin, Hugo De Man 521
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least
Gate Counts
Nguyen Ngoc Binh, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi nennen 527
Session 35
Timing and Power
Chair: Andrew T Yang
Organizers: J White, A T Yang
Analysis of RC Interconnections Under Ramp Input
Andrew B Kahng, Sudhakar Muddu 533
xxvi
35 2
An AWE Technique for Fast Printed Circuit Board Delays
Bernie Sheeh
Chips
Sung-Mo Kang
Chair: Randal E Bryant
Organizers: F, Somenzi, A Kuehlmann
Jerry R Burch
Jeremy Levitt, Kunle Olukotun
State Reduction Using Reversible Rules
C Norris Ip, David L Dill
Alberto Sangiovanni-Vincentelli
Chair: Sean Murphy
Organizer: S Murphy
Dennis Wilson
Chair: Rajiv Jain
Organizers: S Trimberger, P Duncan
A A Jerraya, I Bolsens
J Huisken, F Welten
VHDL
Session 39
Analysis and Compilation for Embedded Software
Chair: Steve Tjiang
Organizers: L Lavagno, R Gupta
RC-Interconnect Macromodels for Timing Simulation
Florentin Dartu, Bogdan Tutuianu, Lawrence T Pileggi uuncensenenssnenennneneorstnnennne 544
iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI
Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum,
Session 36
Verification of Sequential Systems
Techniques for Verifying Superscalar Microprocessors
A Scalable Formal Verification Methodology for Pipelined Microprocessors
Formal Verification of Embedded Systems Based on CFSM Networks
Felice Balarin, Harry Hsieh, Attila Jurecska, Luciano Lavagno,
Session 37
Panel: Electronic Connectivity + EDA Data = Electronic Commerce
Panelists: Jeff Allison, Jake Karrfalt, Michael McClure, Preston Roper,
Session 38
Experience with High Level Synthesis
Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis
E Berrebi, P Kission, S Vernalde, S De Troch, J C Herluison, J Fréhel,
FADIC: Architectural Synthesis Applied in IC Design
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using
Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita usnsssensssesesesnansnsnenne 585
Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register
Architectures
Guido Araujo, Sharad Malik, Mike Tien-Chien Lee
xxvii
a Re ©
oy et Exploration of Instruction-Set
ilation and
‚etable Comp
Address Calculation fOr Ret 597
d Jerraya ne
Are iford Liem » Piers Pauling Execution Rate Constraints for Embedded Systems 601
OD lay ae en ccssssssesessesesencsceentrensssvvensasnenasacesessssgssneniecesenasecsessee
is of Operation ansonsten nett :
Ach K Gupta nn Estimation Methods for Hardware/Software Codesign
Efficient Software Pe Sangiovanni-Vince telllenennen
Kei Suzuki, Alberto
Session 40 ae
Timing Modeling and Optimization
Chair: Andrzej J Strojwas
Anne ik
re hit RC ‘Creu Delay Approximation Based on the First Three Moments of the
n =
ulse Response
open Tunuianı, Florentin Dartu, Lawrence Pileggi aeeessenmenssenennenseesuenneennn O2]
Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation
Delay and Transition Time
V Chandramouli Karem A Sakallah ve 617
Optimal Clock Skew Scheduling Tolerant to Process Variations
José Luis Neves, Eby G Fried 623
Session 41
Decision Diagrams and Their Applications
Chair: Rick Rudell
Organizers: A Kuehlmann, F Somenzi
Au Efficient Equivalence Checker for Combinational Circuits
Yusuke Matsunaga 629
High Performance BDD Package By Exploiting Memory Hierarchy
Jagesh V Sanghavi, Rajeev K Ranjan, Robert K Brayton,
Alberto Sangiovanni-Vincentelli 635
Implemention of an Efficient Parallel BDD Package
Tony Stornetta, Forrest Brewer
Word Level Model Checking—Avoiding the Pentium FDIV Error
E M Clarke, M Khaira, X Zhao
nern 641
senses 645
Session 42
Formal Methods
Chair: Carl Pixley
Organizers: B Frye, N Weste
Formal Verification of PowerPC™ Arrays Using Symbolic Trajectory Evaluation
Manish Pandey, Richard Raimi, Derek L Beatty, Randal E Bryant ecsscsscssssssssessessossees 649
RuleBase: an Industry-Oriented Formal Verification Tool
lian Beer, Shoham Ben-David, Cindy Eisner, Avner Landver nennen nn 655
Bit-Level Analysis of an SRT Divider Circuit
Randal E Bryant : : 661
Integrating Formal Verification Methods with A Conventional Project Design Flow
Asgeir Th Eiriksson 666
Session 43 ;
Applications of Hardware/Software Codesign
Chair: Wayne Wolf
izers: D Stark, N Weste
A System Design Methodology for Software/Hardware Co-Development of
Telecommunication Network Applications
Bill Lin
xxviii
43 2
A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded
Architectures
Steven Vercauteren, Bill Lin, Hugo De Man 678
Software Development in a Hardware Simulation Environment
Benny Schnaider, Einat Yogev 684
Compiled HW/SW Co-Simulation
Vojin Zivojnovic, Heinrich Meyr 690
Session 44
Power Estimation and Retiming
Chair: Bill Lin
Organizers: F Somenzi, B Lin
Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation
Diana Marculescu, Radu Marculescu, Massoud Pe@draim ccccccccsscsceccscscscsssesecesssssscesscesseces 696
Energy Characterization based on Clustering
Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin usecescseseneenennasnnsnensoenssenssnnnnn 702
Architectural Retiming: Pipelining Latency-Constrained Circuits
Soha Hassoun, Carl Ebeling 708
Optimizing Systems for Effective Block-Processing: The k-Delay Problem
Kumar N, Lalgudi, Marios C Papaefthymiou, Miodrag Potkonjak sscssecssssseeeserseess 714
Session 45
Technology Dependent Performance Driven Synthesis
Chair: Gabriele Saucier
Co-Chair: Hamid Savoj
Organizers: M Pedram, G Saucier
Optimal Clock Period FPGA Technology Mapping for Sequential Circuits
Peichen Pan, C L Liu 720
Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based
FPGA Design
Jason Cong, Yean-Yow Hwang 726
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based
FPGA Designs
Christian Legl, Bernd Wurth, Klaus Eckl 730
New Algorithms for Gate Sizing: A Comparative Study
Olivier Coudert, Ramsey Haddad, Srilatha Manne 734
Post-Layout Optimization for Deep Submicron Design
Koichi Sato, Masamichi Kawarabayashi, Hideyuki Emura, Naotaka Maeda c0s 000 740
Session 46
Layout Analysis and Optimization
Chair: Alan Cave
Organizers: Y -L Lin, A Domic
Enhanced Network Flow Algorithm for Yield Optimization
Cyrus Bamji, Enrico Malavasi 746
Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects
Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang urenenesennerennenennnnrnennanne 752
Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance
Extraction
A J van Genderen, N P van der Meijs 758
Extracting Circuit Models for Large RC Interconnections That Are Accurate up to a
Predefined Signal Frequency
PJH Elias, N P van der Meijs 764
xxix
48 2
Session 47
Panel: System Synthesis: Can We Meet the Challenges to Come?
Chair: Robert A Walker
Organizer: R Walker
Panelists: Daniel D Gajksi, Raul Camposano, Pierre Paulin, Laurent Bergher,
Barry Shackleford, Randy Steck 770
Session 48
Hardware Description Language Techniques
Chair: Hilary J Kahn
Organizers: D Stark, B Frye
Tutorial: VHDL amp; Verilog Compared amp; Contrasted—Plus Modeled Example Written
in VHDL, Verilog and C
Douglas J Smith 771
VHDL Development System and Coding Standard
Hans Sahm, Claus Mayer, Jérg Pleickhardt, Johannes Schuck, Stefan Späth 777
Session 49
Power Minimization in IC Design
Chair: Massoud Pedram
Organizers: M Pedram, F Somenzi
An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing
De-Sheng Chen, Majid Sarrafzadeh 783
Reducing Power Dissipation after Technology Mapping by Structural Transformations
Bernhard Rohfleisch, Alfred Kélbl, Bernd Wurth 789
Desensitization for Power Reduction in Sequential Circuits
Xiangfeng Chen, Peicheng Pan, C L Liu
Session 50
Advanced Test Solutions
Chair: Sandip Kundu
Organizers: J Rajski, Y Zorian
Serial Fault Emulation
Luc Burgun, Frédéric Reblewski, Gérard Fenelon, Jean Barbier, Olivier Lepape -- - 801
Partial Scan Design Based on Circuit State Information
Dong Xiang, Srikanth Venkataraman, W Kent Fuchs, Janak H Patel 1cssssores 807
Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths
Laurence Goodby, Alex Orailoglu
Session 51
Technology Optimization for Cells and Systems
Chair: DMH Walker
Organizers: J White, R A Rutenbar
Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing
Aurobindo Dasgupta, Ramesh Karri 819
A Methodology for Concurrent Fabrication Process/Cell Library Optimization
Arun N Lokanathan, Jay B Brockman, John E Renaud ernonseososensensensenonsuerenensesenen 825
Computing Parametric Yield Adaptively Using Local Linear Models
Mien Li, Linda Milor 831
XXX |
| any_adam_object | 1 |
| author_corporate | Design Automation Conference (Association for Computing Machinery) Las Vegas, Nev |
| author_corporate_role | aut |
| author_facet | Design Automation Conference (Association for Computing Machinery) Las Vegas, Nev |
| author_sort | Design Automation Conference (Association for Computing Machinery) Las Vegas, Nev |
| building | Verbundindex |
| bvnumber | BV011041968 |
| classification_rvk | SS 1996 |
| ctrlnum | (OCoLC)312601626 (DE-599)BVBBV011041968 |
| discipline | Informatik |
| format | Conference Proceeding Book |
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| genre_facet | Konferenzschrift 1996 Las Vegas Nev. |
| id | DE-604.BV011041968 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T13:20:27Z |
| institution | BVB |
| institution_GND | (DE-588)5190949-2 |
| isbn | 0780333640 0780332946 0780332954 0897917790 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007393546 |
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| physical | XXX, 839 S. Ill., graph. Darst. |
| publishDate | 1996 |
| publishDateSearch | 1996 |
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| publisher | IEEE |
| record_format | marc |
| spelling | Design Automation Conference (Association for Computing Machinery) 33 1996 Las Vegas, Nev. Verfasser (DE-588)5190949-2 aut Proceedings 1996 Las Vegas Convention Center, Las Vegas, NV. ; June 3 - 7, 1996 33rd Design Automation Conference Piscataway, NJ IEEE 1996 XXX, 839 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1996 Las Vegas Nev. gnd-content CAD (DE-588)4069794-0 s DE-604 HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007393546&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings 1996 Las Vegas Convention Center, Las Vegas, NV. ; June 3 - 7, 1996 CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4069794-0 (DE-588)1071861417 |
| title | Proceedings 1996 Las Vegas Convention Center, Las Vegas, NV. ; June 3 - 7, 1996 |
| title_auth | Proceedings 1996 Las Vegas Convention Center, Las Vegas, NV. ; June 3 - 7, 1996 |
| title_exact_search | Proceedings 1996 Las Vegas Convention Center, Las Vegas, NV. ; June 3 - 7, 1996 |
| title_full | Proceedings 1996 Las Vegas Convention Center, Las Vegas, NV. ; June 3 - 7, 1996 33rd Design Automation Conference |
| title_fullStr | Proceedings 1996 Las Vegas Convention Center, Las Vegas, NV. ; June 3 - 7, 1996 33rd Design Automation Conference |
| title_full_unstemmed | Proceedings 1996 Las Vegas Convention Center, Las Vegas, NV. ; June 3 - 7, 1996 33rd Design Automation Conference |
| title_short | Proceedings 1996 |
| title_sort | proceedings 1996 las vegas convention center las vegas nv june 3 7 1996 |
| title_sub | Las Vegas Convention Center, Las Vegas, NV. ; June 3 - 7, 1996 |
| topic | CAD (DE-588)4069794-0 gnd |
| topic_facet | CAD Konferenzschrift 1996 Las Vegas Nev. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007393546&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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