Field programmable logic: smart applications, new paradigms and compilers: proceedings
Gespeichert in:
Format: | Tagungsbericht Buch |
---|---|
Sprache: | English |
Veröffentlicht: |
Berlin u.a.
Springer
1996
|
Schriftenreihe: | Lecture notes in computer science
1142 |
Schlagworte: | |
Online-Zugang: | Inhaltsverzeichnis |
Beschreibung: | X, 432 S. Ill., graph. Darst. |
ISBN: | 3540617302 |
Internformat
MARC
LEADER | 00000nam a2200000 cb4500 | ||
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035 | |a (DE-599)BVBBV011008763 | ||
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084 | |a 28 |2 sdnb | ||
245 | 1 | 0 | |a Field programmable logic: smart applications, new paradigms and compilers |b proceedings |c 6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, September 23 - 25, 1996. Reiner W. Hartenstein ... (eds.) |
246 | 1 | 3 | |a Field-programmable logic: smart applications, new paradigms and compilers |
264 | 1 | |a Berlin u.a. |b Springer |c 1996 | |
300 | |a X, 432 S. |b Ill., graph. Darst. | ||
336 | |b txt |2 rdacontent | ||
337 | |b n |2 rdamedia | ||
338 | |b nc |2 rdacarrier | ||
490 | 1 | |a Lecture notes in computer science |v 1142 | |
650 | 4 | |a Programmable array logic -- Congresses | |
650 | 0 | 7 | |a Gate-Array-Bauelement |0 (DE-588)4113666-4 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Programmierbare logische Anordnung |0 (DE-588)4076369-9 |2 gnd |9 rswk-swf |
655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 1996 |z Darmstadt |2 gnd-content | |
689 | 0 | 0 | |a Programmierbare logische Anordnung |0 (DE-588)4076369-9 |D s |
689 | 0 | 1 | |a Gate-Array-Bauelement |0 (DE-588)4113666-4 |D s |
689 | 0 | |5 DE-604 | |
700 | 1 | |a Hartenstein, Reiner W. |d 1934-2022 |e Sonstige |0 (DE-588)109112660 |4 oth | |
711 | 2 | |a International Workshop on Field Programmable Logic and Applications |n 6 |d 1996 |c Darmstadt |j Sonstige |0 (DE-588)2158157-5 |4 oth | |
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943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007371135 |
Datensatz im Suchindex
_version_ | 1807320485000642560 |
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adam_text |
TABLE
OF
CONTENTS
HIGH-LEVEL
DESIGN
I
PORTABLE
PIPELINE
SYNTHESIS
FOR
FCCMS
.
1
WEINHARDT,
M.
PERFORMANCE-DIRECTED
TECHNOLOGY
MAPPING
FOR
LUT-BASED
FPGAS
-
WHAT
ROLE
DO
DECOMPOSITION
AND
COVERING
PLAY
?
.
14
LEGL,
C.;
ECKL,
K;
WURTH,
B.
NEW
SOFTWARE
AND
HARDWARE
DEVELOPMENT
TOOLS
A
FRAMEWORK
FOR
DEVELOPING
PARAMETRISED
FPGA
LIBRARIES
.
24
LUK,
W.;
GUO,
S.;
SHIRAZI,
N.;
ZHUANG,
N.
FACT:
CO-EVALUATION
ENVIRONMENT
FOR
FPGA
ARCHITECTURE
AND
CAD
SYSTEM
.
34
MIYAZAKI,
T.;
TSUTSUI,
A.;
ISHII,
K.;
OHTA,
N.
AN
UNIVERSAL
CLA
ADDER
GENERATOR
FOR
SRAM-BASED
FPGAS
.
44
STOHMANN,
J.;
BARKE,
E.;
AN
EMULATION
SYSTEM
OF
THE
WASMII:
A
DATA
DRIVEN
COMPUTER
ON
A
VIRTUAL
HARDWARE
.
55
SHIBATA,
Y.;
LING,
X.-P.;
AMANO,
H.
CUSTOM
COMPUTERS
CUSTOM
COMPUTING
MACHINES
VS.
HARDWARE/SOFTWARE
CODESIGN:
FROM
A
GLOBALIZED
POINT
OF
VIEW
.
65
HARTENSTEIN,
R.W.;
BECKER,
J.;
KRESS,
R.
THE
DESIGN
OF
A
COPROCESSOR
BOARD
USING
XILINX'S
XC6200
FPGA
-
AN
EXPERIENCE
REPORT
.
77
LUDWIG,
S.H.-M.
RACE:
RECONFIGURABLE
AND
ADAPTIVE
COMPUTING
ENVIRONMENT
.
87
SMITH,
D.;
BHATIA,
D.
COMPUTING
2-D
DFTS
USING
FPGAS
.
96
DICK,
C.H.
HIGH-LEVEL
DESIGN
II
CAPPARTX:
COMPUTER
AIDED
PROTOTYPING
PARTITIONING
FOR
XILINX
FPGAS,
A
HIERARCHICAL
PARTITIONING
TOOL
FOR
RAPID
PROTOTYPING
.
106
OBER,
U.;
HERPEL,
H.-J.;
GLESNER,
M.
VIII
ARCHITECTURAL
SYNTHESIS
AND
EFFICIENT
CIRCUIT
IMPLEMENTATION
FOR
FIELD
PROGRAMMABLE
GATE
ARRAYS
.
116
TRAINOR,
D.W.;
WOODS,
R.F.
RAPID
-
RECONFIGURABLE
PIPELINED
DATAPATH
.
126
EBELING,
C.;
CRONQUIST,
D.C.;
FRANKLIN,
P.
APPLICATIONS
SOLVING
SATISFIABILITY
PROBLEMS
ON
FPGAS
.
136
SUYAMA,
T.;
YOKOO,
M.;
SAWADA,
H.
FPGA
IMPLEMENTATION
OF
THE
BLOCK-MATCHING
ALGORITHM
FOR
MOTION
ESTIMATION
IN
IMAGE
CODING
.
146
SANZ,
C.;
DE
ZULUETA,
L;
MENESES,
J.M.
PARALLEL
CRC
COMPUTATION
IN
FPGAS
.
156
BRAUN,
M.;
FRIEDRICH,
J.;
GRUN,
T.;
LEMBERT,
J.
COHERENT
DEMODULATION
WITH
FPGAS
.
166
MEYER-BASE,
U.
HARDWARE
/
SOFTWARE
CO-DESIGN
THE
TRIANUS
SYSTEM
AND
ITS
APPLICATION
TO
CUSTOM
COMPUTING
.
176
GEHRING,
S.;
LUDWIG,
S.
LOGIC
SYNTHESIS
FOR
FPGAS
USING
A
MIXED
EXCLUSIVE
/
INCLUSIVE
OR
FORM
.
185
LESTER,
N.;
SAUL,
J.
FLEXIBLE
CODESIGN
TARGET
ARCHITECTURE
FOR
EARLY
PROTOTYPING
OF
CMIST
SYSTEMS
.
193
TAMMEMDE,
K.;
O'NILS,
M.;
HEMANI,
A.
ASIC
EMULATORS
ETC.
ATTEMPT
1:
A
RECONFIGURABLE
MULTIPROCESSOR
TESTBED
.
200
INOUE,
K.;
KISUKI,
T;
OKUNO,
M.;
SHIMIZU,
E;
TERASAWA,
T.;
AMANO,
H.
A
SLOW
MOTION
ENGINE
FOR
THE
ANALYSIS
OF
FPGA-BASED
PROTOTYPES
.
210
JANZEN,
N.;
RAMMIG,
F.J.
VENDOR
SESSION
IMPLEMENTING
RECONFIGURABLE
DATAPATHS
IN
FPGAS
FOR
ADAPTIVE
FILTER
DESIGN
.220
HESENER,
A.
A
FAST
CONSTANT
COEFFICIENT
MULTIPLIER
FOR
THE
XC6200
.
230
KEAN,
T.;
NEW,
B.;
SLOUS,
B.
IX
KEY
ISSUES
FOR
USER
ACCEPTANCE
OF
FPGA
DESIGN
TOOLS
.
237
DITZINGER,
A.;
REMME,
R.
INDUSTRIAL
APPLICATIONS
AND
EXPERIENCES
RECONFIGURABLE
DSP
DEMONSTRATORS
FOR
THE
DEVELOPMENT
OF
SPACECRAFT
PAYLOAD
PROCESSORS
.
242
CAMBRIDGE,
B.L.;
CORNFIELD,
P.S.;
NAUNTON,
S.
RECONFIGURABLE
LOGIC
BASED
FIBRE
CHANNEL
NETWORK
CARD
WITH
SUB
2
MICRO-SECOND
RAW
LATENCY
.
252
CASSELMAN,
S.
AN
ASYNCHRONOUS
TRANSFER
MODE
(ATM)
STREAM
DEMULTIPLEXER
AND
SWITCH
.
260
HADDY,
J.R.;
SKELLEM,
D.J.
RECONFIGURATION
ASPECTS
OPTICALLY
RECONFIGURABLE
FPGAS:
IS
THIS
A
FUTURE
TREND
?
.
270
VASILKO,
M.;
AIT-BOUDAOUD,
D.
CCSIMP
-
AN
INSTRUCTION-LEVEL
CUSTOM-CONFIGURABLE
PROCESSOR
FORFPLDS
.
280
SALCIC,
Z.;
MAUNDER,
B.
ARCHITECTURAL
SYNTHESIS
TECHNIQUES
FOR
DYNAMICALLY
RECONFIGURABLE
LOGIC
.
290
VASILKO,
M.;
AIT-BOUDAOUD,
D.
FAST
RECONFIGURABLE
CROSSBAR
SWITCHING
IN
FPGAS
.
297
EGGERS,
H;
LYSAGHT,
P.;
DICK,
H.;
MCGREGOR,
G.
CAD
USER
EXPERIENCES
GROWABLE
FPGA
MACRO
GENERATOR
.
307
YAS
AR,
G.;
DEVINS,
J.;
TSYRKINA,
Y.;
STADTLANDER,
G.;
MILLHAM,
E.
ARCHITECTURAL
STRATEGIES
FOR
IMPLEMENTING
AN
IMAGE
PROCESSING
ALGORITHM
ON
XC6000
FPGA
.
317
HERON,
J.P.;
WOODS,
R.F.
A
VIRTUAL
HARDWARE
OPERATING
SYSTEM
FOR
THE
XILINX
XC6200
.
327
BREBNER,
G.
AN
EXPERIMENTAL
PROGRAMMABLE
ENVIRONMENT
FOR
PROTOTYPING
DIGITAL
CIRCUITS
.
337
TROST,
A.;
KUZNAR,
R.;
ZEMVA,
A.;
ZAJC,
B.
MIGRATION
FROM
SCHEMATIC-BASED
DESIGNS
TO
A
VHDL
SYNTHESIS
ENVIRONMENT
.
346
GSCHWIND,
M.;
MAUTNER,
C.
X
MISCELLANEOUS
ASIC
DESIGN
AND
FPGA
DESIGN:
A
UNIFIED
DESIGN
METHODOLOGY
APPLIED
TO
DIFFERENT
TECHNOLOGIES
.
356
BALBONI,
A.;
VALENTI,
L.
FIR
FILTERING
WITH
FPGAS
USING
QUADRATURE
SIGMA-DELTA
MODULATION
ENCODING
.
361
DICK,
C.H.;
HARRIS,
F.
A
NEW
FPGA
TECHNOLOGY
MAPPING
APPROACH
BY
CLUSTER
MERGING
.
366
YI,
K.;
JHON,
C.-S.
AN
EPLD
BASED
TRANSIENT
RECORDER
FOR
SIMULATION
OF
VIDEO
SIGNAL
PROCESSING
DEVICES
IN
A
VHDL
ENVIRONMENT
CLOSE
TO
SYSTEM
LEVEL
CONDITIONS
.
371
LARSSON,
L.
CONVOLUTIONAL
ERROR
DECODING
WITH
FPGAS
.
376
MEYER-BASE,
U.
METASTABILITY
CHARACTERISTICS
TESTING
FOR
PROGRAMMABLE
LOGIC
DESIGN
.
381
ROGINA,
B.M.;
SKALA,
K.;
VOJNOVIC,
B.
IMPLEMENTING
SIGMA
DELTA
MODULATOR
PROTOTYPE
DESIGNS
ON
AN
FPGA
.
389
ROWLEY,
K.
;
LYDEN,
C.
DESIGN
OF
A
VME
PARAMETRIZED
LIBRARY
FOR
FPGAS
.
394
RUIZ,
J.L.;
TORROJA,
Y;
GARCIA,
J.L.
DEVELOPMENT
OF
A
TELEPHONE
ANSWERING
MACHINE
IN
A
LAB
-
FPGAS
IN
EDUCATION
.
400
SCHUMACHER,
G.;
JOSKO,
B.;
WAGNER,
G.;
RADETZJD,
M.
FPGA
DESIGN
MIGRATION:
SOME
REMARKS
.
405
TCHOUMATCHENKO,
V.;
VASSILEVA,
T.;
RIBAS,
R.;
GUYOT,
A.
CONCURRENT
DESIGN
OF
HARDWARE/SOFTWARE
DEDICATED
SYSTEMS
.410
PILLEMENT,
S.;
TORRES,
L.;
ROBERT,
M.;
CAMBON,
G.
THE
IMPLEMENTATION
OF
A
FIELD
PROGRAMMABLE
LOGIC
BASED
CO-PROCESSOR
FOR
THE
ACCELERATION
OF
DISCRETE
EVENT
SIMULATORS
.
415
TOUHAFI,
A.;
BRISSINCK,
W;
DIRKX,
E.F.
COMPUTING
WEIGHT
DISTRIBUTIONS
OF
BINARY
LINEAR
BLOCK
CODES
ONACCM
.
425
WEINHARDT,
M.
AUTHOR
INDEX
.
431 |
any_adam_object | 1 |
author_GND | (DE-588)109112660 |
building | Verbundindex |
bvnumber | BV011008763 |
callnumber-first | T - Technology |
callnumber-label | TK7868 |
callnumber-raw | TK7868.L6I56 1996 |
callnumber-search | TK7868.L6I56 1996 |
callnumber-sort | TK 47868 L6 I56 41996 |
callnumber-subject | TK - Electrical and Nuclear Engineering |
classification_rvk | SS 1996 SS 4800 |
classification_tum | DAT 540f |
ctrlnum | (OCoLC)56853461 (DE-599)BVBBV011008763 |
dewey-full | 621.39/520 621.39/5 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.39/5 20 621.39/5 |
dewey-search | 621.39/5 20 621.39/5 |
dewey-sort | 3621.39 15 220 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
format | Conference Proceeding Book |
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genre | (DE-588)1071861417 Konferenzschrift 1996 Darmstadt gnd-content |
genre_facet | Konferenzschrift 1996 Darmstadt |
id | DE-604.BV011008763 |
illustrated | Illustrated |
indexdate | 2024-08-14T00:25:26Z |
institution | BVB |
institution_GND | (DE-588)2158157-5 |
isbn | 3540617302 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007371135 |
oclc_num | 56853461 |
open_access_boolean | |
owner | DE-91 DE-BY-TUM DE-91G DE-BY-TUM DE-384 DE-739 DE-19 DE-BY-UBM DE-29T DE-20 DE-706 DE-634 DE-83 |
owner_facet | DE-91 DE-BY-TUM DE-91G DE-BY-TUM DE-384 DE-739 DE-19 DE-BY-UBM DE-29T DE-20 DE-706 DE-634 DE-83 |
physical | X, 432 S. Ill., graph. Darst. |
publishDate | 1996 |
publishDateSearch | 1996 |
publishDateSort | 1996 |
publisher | Springer |
record_format | marc |
series | Lecture notes in computer science |
series2 | Lecture notes in computer science |
spelling | Field programmable logic: smart applications, new paradigms and compilers proceedings 6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, September 23 - 25, 1996. Reiner W. Hartenstein ... (eds.) Field-programmable logic: smart applications, new paradigms and compilers Berlin u.a. Springer 1996 X, 432 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 1142 Programmable array logic -- Congresses Gate-Array-Bauelement (DE-588)4113666-4 gnd rswk-swf Programmierbare logische Anordnung (DE-588)4076369-9 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1996 Darmstadt gnd-content Programmierbare logische Anordnung (DE-588)4076369-9 s Gate-Array-Bauelement (DE-588)4113666-4 s DE-604 Hartenstein, Reiner W. 1934-2022 Sonstige (DE-588)109112660 oth International Workshop on Field Programmable Logic and Applications 6 1996 Darmstadt Sonstige (DE-588)2158157-5 oth Lecture notes in computer science 1142 (DE-604)BV000000607 1142 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007371135&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
spellingShingle | Field programmable logic: smart applications, new paradigms and compilers proceedings Lecture notes in computer science Programmable array logic -- Congresses Gate-Array-Bauelement (DE-588)4113666-4 gnd Programmierbare logische Anordnung (DE-588)4076369-9 gnd |
subject_GND | (DE-588)4113666-4 (DE-588)4076369-9 (DE-588)1071861417 |
title | Field programmable logic: smart applications, new paradigms and compilers proceedings |
title_alt | Field-programmable logic: smart applications, new paradigms and compilers |
title_auth | Field programmable logic: smart applications, new paradigms and compilers proceedings |
title_exact_search | Field programmable logic: smart applications, new paradigms and compilers proceedings |
title_full | Field programmable logic: smart applications, new paradigms and compilers proceedings 6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, September 23 - 25, 1996. Reiner W. Hartenstein ... (eds.) |
title_fullStr | Field programmable logic: smart applications, new paradigms and compilers proceedings 6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, September 23 - 25, 1996. Reiner W. Hartenstein ... (eds.) |
title_full_unstemmed | Field programmable logic: smart applications, new paradigms and compilers proceedings 6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, September 23 - 25, 1996. Reiner W. Hartenstein ... (eds.) |
title_short | Field programmable logic: smart applications, new paradigms and compilers |
title_sort | field programmable logic smart applications new paradigms and compilers proceedings |
title_sub | proceedings |
topic | Programmable array logic -- Congresses Gate-Array-Bauelement (DE-588)4113666-4 gnd Programmierbare logische Anordnung (DE-588)4076369-9 gnd |
topic_facet | Programmable array logic -- Congresses Gate-Array-Bauelement Programmierbare logische Anordnung Konferenzschrift 1996 Darmstadt |
url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007371135&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
volume_link | (DE-604)BV000000607 |
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