Architecture and implementation of PIM m:
Abstract: "In the FGCS project, we have developed a parallel inference machine, PIM/m, as one of the final products of the project. PIM/m has up to 256 processor elements (PEs) connected by a 16 x 16 mesh network, while its predecessor, Multi-PSI/v2, has 64 PEs. A PE has three custom VLSI chips...
Gespeichert in:
Format: | Buch |
---|---|
Sprache: | English |
Veröffentlicht: |
Tokyo, Japan
1992
|
Schriftenreihe: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
742 |
Schlagworte: | |
Zusammenfassung: | Abstract: "In the FGCS project, we have developed a parallel inference machine, PIM/m, as one of the final products of the project. PIM/m has up to 256 processor elements (PEs) connected by a 16 x 16 mesh network, while its predecessor, Multi-PSI/v2, has 64 PEs. A PE has three custom VLSI chips, one of which is a pipelined microprocessor having special mechanisms for KL1 execution, such as pipelined data typing and dereference. As for the KL1 implementation on PIM/m, we took much care of garbage collection and introduced various techniques, such as incremental reclamation of local and remote garbage. Especially, a hardware mechanism to support the local garbage collection greatly contributes to reducing the overhead and achieving high peak performance, 615 KLIPS in append on single processor Sustained performance of single processor is also improved, and is approximately twice as high as that of Multi-PSI/v2. This improvement and the enlargement of the system scale cooperatively enhance the total system performance, and make PIM/m 5 to 10 times as fast as Multi-PSI/v2. |
Beschreibung: | 11 S. |
Internformat
MARC
LEADER | 00000nam a2200000 cb4500 | ||
---|---|---|---|
001 | BV010957969 | ||
003 | DE-604 | ||
005 | 00000000000000.0 | ||
007 | t | ||
008 | 960919s1992 |||| 00||| engod | ||
035 | |a (OCoLC)27807741 | ||
035 | |a (DE-599)BVBBV010957969 | ||
040 | |a DE-604 |b ger |e rakddb | ||
041 | 0 | |a eng | |
049 | |a DE-91G | ||
245 | 1 | 0 | |a Architecture and implementation of PIM m |c by H. Nakashima ... |
264 | 1 | |a Tokyo, Japan |c 1992 | |
300 | |a 11 S. | ||
336 | |b txt |2 rdacontent | ||
337 | |b n |2 rdamedia | ||
338 | |b nc |2 rdacarrier | ||
490 | 1 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 742 | |
520 | 3 | |a Abstract: "In the FGCS project, we have developed a parallel inference machine, PIM/m, as one of the final products of the project. PIM/m has up to 256 processor elements (PEs) connected by a 16 x 16 mesh network, while its predecessor, Multi-PSI/v2, has 64 PEs. A PE has three custom VLSI chips, one of which is a pipelined microprocessor having special mechanisms for KL1 execution, such as pipelined data typing and dereference. As for the KL1 implementation on PIM/m, we took much care of garbage collection and introduced various techniques, such as incremental reclamation of local and remote garbage. Especially, a hardware mechanism to support the local garbage collection greatly contributes to reducing the overhead and achieving high peak performance, 615 KLIPS in append on single processor | |
520 | 3 | |a Sustained performance of single processor is also improved, and is approximately twice as high as that of Multi-PSI/v2. This improvement and the enlargement of the system scale cooperatively enhance the total system performance, and make PIM/m 5 to 10 times as fast as Multi-PSI/v2. | |
650 | 4 | |a Fifth generation computers | |
700 | 1 | |a Nakashima, Hiroshi |e Sonstige |4 oth | |
830 | 0 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 742 |w (DE-604)BV010923438 |9 742 | |
999 | |a oai:aleph.bib-bvb.de:BVB01-007329914 |
Datensatz im Suchindex
_version_ | 1804125445449318400 |
---|---|
any_adam_object | |
building | Verbundindex |
bvnumber | BV010957969 |
ctrlnum | (OCoLC)27807741 (DE-599)BVBBV010957969 |
format | Book |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02027nam a2200301 cb4500</leader><controlfield tag="001">BV010957969</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">960919s1992 |||| 00||| engod</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)27807741</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV010957969</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Architecture and implementation of PIM m</subfield><subfield code="c">by H. Nakashima ...</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Tokyo, Japan</subfield><subfield code="c">1992</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">11 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">742</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Abstract: "In the FGCS project, we have developed a parallel inference machine, PIM/m, as one of the final products of the project. PIM/m has up to 256 processor elements (PEs) connected by a 16 x 16 mesh network, while its predecessor, Multi-PSI/v2, has 64 PEs. A PE has three custom VLSI chips, one of which is a pipelined microprocessor having special mechanisms for KL1 execution, such as pipelined data typing and dereference. As for the KL1 implementation on PIM/m, we took much care of garbage collection and introduced various techniques, such as incremental reclamation of local and remote garbage. Especially, a hardware mechanism to support the local garbage collection greatly contributes to reducing the overhead and achieving high peak performance, 615 KLIPS in append on single processor</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Sustained performance of single processor is also improved, and is approximately twice as high as that of Multi-PSI/v2. This improvement and the enlargement of the system scale cooperatively enhance the total system performance, and make PIM/m 5 to 10 times as fast as Multi-PSI/v2.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fifth generation computers</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Nakashima, Hiroshi</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">742</subfield><subfield code="w">(DE-604)BV010923438</subfield><subfield code="9">742</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-007329914</subfield></datafield></record></collection> |
id | DE-604.BV010957969 |
illustrated | Not Illustrated |
indexdate | 2024-07-09T18:01:40Z |
institution | BVB |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007329914 |
oclc_num | 27807741 |
open_access_boolean | |
owner | DE-91G DE-BY-TUM |
owner_facet | DE-91G DE-BY-TUM |
physical | 11 S. |
publishDate | 1992 |
publishDateSearch | 1992 |
publishDateSort | 1992 |
record_format | marc |
series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
spelling | Architecture and implementation of PIM m by H. Nakashima ... Tokyo, Japan 1992 11 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 742 Abstract: "In the FGCS project, we have developed a parallel inference machine, PIM/m, as one of the final products of the project. PIM/m has up to 256 processor elements (PEs) connected by a 16 x 16 mesh network, while its predecessor, Multi-PSI/v2, has 64 PEs. A PE has three custom VLSI chips, one of which is a pipelined microprocessor having special mechanisms for KL1 execution, such as pipelined data typing and dereference. As for the KL1 implementation on PIM/m, we took much care of garbage collection and introduced various techniques, such as incremental reclamation of local and remote garbage. Especially, a hardware mechanism to support the local garbage collection greatly contributes to reducing the overhead and achieving high peak performance, 615 KLIPS in append on single processor Sustained performance of single processor is also improved, and is approximately twice as high as that of Multi-PSI/v2. This improvement and the enlargement of the system scale cooperatively enhance the total system performance, and make PIM/m 5 to 10 times as fast as Multi-PSI/v2. Fifth generation computers Nakashima, Hiroshi Sonstige oth Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 742 (DE-604)BV010923438 742 |
spellingShingle | Architecture and implementation of PIM m Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report Fifth generation computers |
title | Architecture and implementation of PIM m |
title_auth | Architecture and implementation of PIM m |
title_exact_search | Architecture and implementation of PIM m |
title_full | Architecture and implementation of PIM m by H. Nakashima ... |
title_fullStr | Architecture and implementation of PIM m by H. Nakashima ... |
title_full_unstemmed | Architecture and implementation of PIM m by H. Nakashima ... |
title_short | Architecture and implementation of PIM m |
title_sort | architecture and implementation of pim m |
topic | Fifth generation computers |
topic_facet | Fifth generation computers |
volume_link | (DE-604)BV010923438 |
work_keys_str_mv | AT nakashimahiroshi architectureandimplementationofpimm |