Applying inter-cluster shared memory architecture to a parallel inference machine:
Abstract: "This paper discusses the feasibility of a parallel inference machine with the inter-cluster shared memory architecture in stead [sic] of the message passing mechanism. The discussion includes two possible memory architectures which fit to the memory access features, and the system so...
Gespeichert in:
| Format: | Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Tokyo, Japan
1992
|
| Schriftenreihe: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
769 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "This paper discusses the feasibility of a parallel inference machine with the inter-cluster shared memory architecture in stead [sic] of the message passing mechanism. The discussion includes two possible memory architectures which fit to the memory access features, and the system software under the proposed memory architecture. Although the main objective is the smaller latency of the remote memory access, additional advantages are also discussed." |
| Beschreibung: | 6 S. |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV010956781 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 960919s1992 |||| 00||| engod | ||
| 035 | |a (OCoLC)27424315 | ||
| 035 | |a (DE-599)BVBBV010956781 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G | ||
| 245 | 1 | 0 | |a Applying inter-cluster shared memory architecture to a parallel inference machine |c by H. Sakai ... |
| 264 | 1 | |a Tokyo, Japan |c 1992 | |
| 300 | |a 6 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 769 | |
| 520 | 3 | |a Abstract: "This paper discusses the feasibility of a parallel inference machine with the inter-cluster shared memory architecture in stead [sic] of the message passing mechanism. The discussion includes two possible memory architectures which fit to the memory access features, and the system software under the proposed memory architecture. Although the main objective is the smaller latency of the remote memory access, additional advantages are also discussed." | |
| 650 | 4 | |a Fifth generation computers | |
| 650 | 4 | |a KL1 (Computer program language) | |
| 650 | 4 | |a Logic programming | |
| 650 | 4 | |a Parallel processing (Electronic computers) | |
| 700 | 1 | |a Sakai, Hiroshi |e Sonstige |4 oth | |
| 830 | 0 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 769 |w (DE-604)BV010923438 |9 769 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-007328876 | ||
Datensatz im Suchindex
| _version_ | 1804125444058906624 |
|---|---|
| any_adam_object | |
| building | Verbundindex |
| bvnumber | BV010956781 |
| ctrlnum | (OCoLC)27424315 (DE-599)BVBBV010956781 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01563nam a2200325 cb4500</leader><controlfield tag="001">BV010956781</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">960919s1992 |||| 00||| engod</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)27424315</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV010956781</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Applying inter-cluster shared memory architecture to a parallel inference machine</subfield><subfield code="c">by H. Sakai ...</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Tokyo, Japan</subfield><subfield code="c">1992</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">6 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">769</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Abstract: "This paper discusses the feasibility of a parallel inference machine with the inter-cluster shared memory architecture in stead [sic] of the message passing mechanism. The discussion includes two possible memory architectures which fit to the memory access features, and the system software under the proposed memory architecture. Although the main objective is the smaller latency of the remote memory access, additional advantages are also discussed."</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fifth generation computers</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">KL1 (Computer program language)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic programming</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Parallel processing (Electronic computers)</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Sakai, Hiroshi</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">769</subfield><subfield code="w">(DE-604)BV010923438</subfield><subfield code="9">769</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-007328876</subfield></datafield></record></collection> |
| id | DE-604.BV010956781 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:01:39Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007328876 |
| oclc_num | 27424315 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 6 S. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| spelling | Applying inter-cluster shared memory architecture to a parallel inference machine by H. Sakai ... Tokyo, Japan 1992 6 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 769 Abstract: "This paper discusses the feasibility of a parallel inference machine with the inter-cluster shared memory architecture in stead [sic] of the message passing mechanism. The discussion includes two possible memory architectures which fit to the memory access features, and the system software under the proposed memory architecture. Although the main objective is the smaller latency of the remote memory access, additional advantages are also discussed." Fifth generation computers KL1 (Computer program language) Logic programming Parallel processing (Electronic computers) Sakai, Hiroshi Sonstige oth Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 769 (DE-604)BV010923438 769 |
| spellingShingle | Applying inter-cluster shared memory architecture to a parallel inference machine Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report Fifth generation computers KL1 (Computer program language) Logic programming Parallel processing (Electronic computers) |
| title | Applying inter-cluster shared memory architecture to a parallel inference machine |
| title_auth | Applying inter-cluster shared memory architecture to a parallel inference machine |
| title_exact_search | Applying inter-cluster shared memory architecture to a parallel inference machine |
| title_full | Applying inter-cluster shared memory architecture to a parallel inference machine by H. Sakai ... |
| title_fullStr | Applying inter-cluster shared memory architecture to a parallel inference machine by H. Sakai ... |
| title_full_unstemmed | Applying inter-cluster shared memory architecture to a parallel inference machine by H. Sakai ... |
| title_short | Applying inter-cluster shared memory architecture to a parallel inference machine |
| title_sort | applying inter cluster shared memory architecture to a parallel inference machine |
| topic | Fifth generation computers KL1 (Computer program language) Logic programming Parallel processing (Electronic computers) |
| topic_facet | Fifth generation computers KL1 (Computer program language) Logic programming Parallel processing (Electronic computers) |
| volume_link | (DE-604)BV010923438 |
| work_keys_str_mv | AT sakaihiroshi applyinginterclustersharedmemoryarchitecturetoaparallelinferencemachine |