The unique features of PIM k: a parallel inference machine with hierarchical cache system
Abstract: "This paper presents the unique features of a multiprocessor system, its hierarchical cache system, dedicated debug supports and performance evaluation mechanisms. For the hierachical cache system, we present general consideration to extend a well known one-level cache protocol for th...
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| Main Authors: | , , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Tokyo, Japan
1992
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| Series: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
767 |
| Subjects: | |
| Summary: | Abstract: "This paper presents the unique features of a multiprocessor system, its hierarchical cache system, dedicated debug supports and performance evaluation mechanisms. For the hierachical cache system, we present general consideration to extend a well known one-level cache protocol for the two-level cache. The new feature of it is a special replacement algorithm which keeps multi-level-inclusion property. For the second feature, we present novel mechanisms by which we can debug and evaluate the multiprocessor effectively. The mechanisms guarantee the same consequence with the same input." |
| Physical Description: | 15 S. |
Staff View
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| 264 | 1 | |a Tokyo, Japan |c 1992 | |
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| 520 | 3 | |a Abstract: "This paper presents the unique features of a multiprocessor system, its hierarchical cache system, dedicated debug supports and performance evaluation mechanisms. For the hierachical cache system, we present general consideration to extend a well known one-level cache protocol for the two-level cache. The new feature of it is a special replacement algorithm which keeps multi-level-inclusion property. For the second feature, we present novel mechanisms by which we can debug and evaluate the multiprocessor effectively. The mechanisms guarantee the same consequence with the same input." | |
| 650 | 4 | |a Fifth generation computers | |
| 650 | 4 | |a Multiprocessors | |
| 650 | 4 | |a Parallel processing (Electronic computers) | |
| 700 | 1 | |a Isobe, Shouzou |e Verfasser |4 aut | |
| 700 | 1 | |a Sakai, Hiroshi |e Verfasser |4 aut | |
| 830 | 0 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 767 |w (DE-604)BV010923438 |9 767 | |
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Record in the Search Index
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| author | Asano, Shigehiro Isobe, Shouzou Sakai, Hiroshi |
| author_facet | Asano, Shigehiro Isobe, Shouzou Sakai, Hiroshi |
| author_role | aut aut aut |
| author_sort | Asano, Shigehiro |
| author_variant | s a sa s i si h s hs |
| building | Verbundindex |
| bvnumber | BV010956738 |
| ctrlnum | (OCoLC)27424372 (DE-599)BVBBV010956738 |
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| id | DE-604.BV010956738 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:01:39Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007328837 |
| oclc_num | 27424372 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 15 S. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| spelling | Asano, Shigehiro Verfasser aut The unique features of PIM k a parallel inference machine with hierarchical cache system by S. Asano, S. Isobe & H. Sakai Tokyo, Japan 1992 15 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 767 Abstract: "This paper presents the unique features of a multiprocessor system, its hierarchical cache system, dedicated debug supports and performance evaluation mechanisms. For the hierachical cache system, we present general consideration to extend a well known one-level cache protocol for the two-level cache. The new feature of it is a special replacement algorithm which keeps multi-level-inclusion property. For the second feature, we present novel mechanisms by which we can debug and evaluate the multiprocessor effectively. The mechanisms guarantee the same consequence with the same input." Fifth generation computers Multiprocessors Parallel processing (Electronic computers) Isobe, Shouzou Verfasser aut Sakai, Hiroshi Verfasser aut Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 767 (DE-604)BV010923438 767 |
| spellingShingle | Asano, Shigehiro Isobe, Shouzou Sakai, Hiroshi The unique features of PIM k a parallel inference machine with hierarchical cache system Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report Fifth generation computers Multiprocessors Parallel processing (Electronic computers) |
| title | The unique features of PIM k a parallel inference machine with hierarchical cache system |
| title_auth | The unique features of PIM k a parallel inference machine with hierarchical cache system |
| title_exact_search | The unique features of PIM k a parallel inference machine with hierarchical cache system |
| title_full | The unique features of PIM k a parallel inference machine with hierarchical cache system by S. Asano, S. Isobe & H. Sakai |
| title_fullStr | The unique features of PIM k a parallel inference machine with hierarchical cache system by S. Asano, S. Isobe & H. Sakai |
| title_full_unstemmed | The unique features of PIM k a parallel inference machine with hierarchical cache system by S. Asano, S. Isobe & H. Sakai |
| title_short | The unique features of PIM k |
| title_sort | the unique features of pim k a parallel inference machine with hierarchical cache system |
| title_sub | a parallel inference machine with hierarchical cache system |
| topic | Fifth generation computers Multiprocessors Parallel processing (Electronic computers) |
| topic_facet | Fifth generation computers Multiprocessors Parallel processing (Electronic computers) |
| volume_link | (DE-604)BV010923438 |
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