An intelligent cache memory chip suitable for logical inference:
Saved in:
| Format: | Book |
|---|---|
| Language: | English |
| Published: |
Tokyo, Japan
1991
|
| Series: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
709 |
| Subjects: | |
| Physical Description: | 34 S. |
Staff View
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| id | DE-604.BV010956046 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:01:38Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007328228 |
| oclc_num | 26483714 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 34 S. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| spelling | An intelligent cache memory chip suitable for logical inference by K. Yasuda ... Tokyo, Japan 1991 34 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 709 Cache memory Fifth generation computers Yasuda, Kenichi Sonstige oth Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 709 (DE-604)BV010923438 709 |
| spellingShingle | An intelligent cache memory chip suitable for logical inference Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report Cache memory Fifth generation computers |
| title | An intelligent cache memory chip suitable for logical inference |
| title_auth | An intelligent cache memory chip suitable for logical inference |
| title_exact_search | An intelligent cache memory chip suitable for logical inference |
| title_full | An intelligent cache memory chip suitable for logical inference by K. Yasuda ... |
| title_fullStr | An intelligent cache memory chip suitable for logical inference by K. Yasuda ... |
| title_full_unstemmed | An intelligent cache memory chip suitable for logical inference by K. Yasuda ... |
| title_short | An intelligent cache memory chip suitable for logical inference |
| title_sort | an intelligent cache memory chip suitable for logical inference |
| topic | Cache memory Fifth generation computers |
| topic_facet | Cache memory Fifth generation computers |
| volume_link | (DE-604)BV010923438 |
| work_keys_str_mv | AT yasudakenichi anintelligentcachememorychipsuitableforlogicalinference |