Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine:
Abstract: "Co-HLEX is a cooperative hierarchical layout problem solver developed as an application program of parallel inference machines; Multi-PSI and PIM. The kernel of co-HLEX is a hierarchical recursive concurrent theorem prover nicknamed HRCTL. Due to its recursive nature, HRCTL has a siz...
Saved in:
| Main Authors: | , |
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| Format: | Book |
| Language: | English |
| Published: |
Tokyo, Japan
1991
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| Series: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
707 |
| Subjects: | |
| Summary: | Abstract: "Co-HLEX is a cooperative hierarchical layout problem solver developed as an application program of parallel inference machines; Multi-PSI and PIM. The kernel of co-HLEX is a hierarchical recursive concurrent theorem prover nicknamed HRCTL. Due to its recursive nature, HRCTL has a size of only O(1,000) lines in KL1; the kernel language of ICOT. Due to its stream-parallel and distributed-memory architecture, nearly linear time complexity could be attained. Moreover, shape and wire abutment among modules running in parallel could be made through message passing cooperations. In this paper, a brief overview of co-HLEX is given with its application to bipolar-analog LSI layout." |
| Physical Description: | 10 S. |
Staff View
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV010956036 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 960918s1991 |||| 00||| engod | ||
| 035 | |a (OCoLC)26483682 | ||
| 035 | |a (DE-599)BVBBV010956036 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G | ||
| 100 | 1 | |a Watanabe, Tosahinori |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine |c by T. Watanabe & K. Komatsu |
| 264 | 1 | |a Tokyo, Japan |c 1991 | |
| 300 | |a 10 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 707 | |
| 520 | 3 | |a Abstract: "Co-HLEX is a cooperative hierarchical layout problem solver developed as an application program of parallel inference machines; Multi-PSI and PIM. The kernel of co-HLEX is a hierarchical recursive concurrent theorem prover nicknamed HRCTL. Due to its recursive nature, HRCTL has a size of only O(1,000) lines in KL1; the kernel language of ICOT. Due to its stream-parallel and distributed-memory architecture, nearly linear time complexity could be attained. Moreover, shape and wire abutment among modules running in parallel could be made through message passing cooperations. In this paper, a brief overview of co-HLEX is given with its application to bipolar-analog LSI layout." | |
| 650 | 4 | |a Fifth generation computers | |
| 700 | 1 | |a Komatsu, Keiko |e Verfasser |4 aut | |
| 830 | 0 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 707 |w (DE-604)BV010923438 |9 707 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-007328218 | ||
Record in the Search Index
| _version_ | 1804125443213754368 |
|---|---|
| any_adam_object | |
| author | Watanabe, Tosahinori Komatsu, Keiko |
| author_facet | Watanabe, Tosahinori Komatsu, Keiko |
| author_role | aut aut |
| author_sort | Watanabe, Tosahinori |
| author_variant | t w tw k k kk |
| building | Verbundindex |
| bvnumber | BV010956036 |
| ctrlnum | (OCoLC)26483682 (DE-599)BVBBV010956036 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01718nam a2200301 cb4500</leader><controlfield tag="001">BV010956036</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">960918s1991 |||| 00||| engod</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)26483682</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV010956036</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Watanabe, Tosahinori</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine</subfield><subfield code="c">by T. Watanabe & K. Komatsu</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Tokyo, Japan</subfield><subfield code="c">1991</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">10 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">707</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Abstract: "Co-HLEX is a cooperative hierarchical layout problem solver developed as an application program of parallel inference machines; Multi-PSI and PIM. The kernel of co-HLEX is a hierarchical recursive concurrent theorem prover nicknamed HRCTL. Due to its recursive nature, HRCTL has a size of only O(1,000) lines in KL1; the kernel language of ICOT. Due to its stream-parallel and distributed-memory architecture, nearly linear time complexity could be attained. Moreover, shape and wire abutment among modules running in parallel could be made through message passing cooperations. In this paper, a brief overview of co-HLEX is given with its application to bipolar-analog LSI layout."</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fifth generation computers</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Komatsu, Keiko</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">707</subfield><subfield code="w">(DE-604)BV010923438</subfield><subfield code="9">707</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-007328218</subfield></datafield></record></collection> |
| id | DE-604.BV010956036 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:01:38Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007328218 |
| oclc_num | 26483682 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 10 S. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| spelling | Watanabe, Tosahinori Verfasser aut Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine by T. Watanabe & K. Komatsu Tokyo, Japan 1991 10 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 707 Abstract: "Co-HLEX is a cooperative hierarchical layout problem solver developed as an application program of parallel inference machines; Multi-PSI and PIM. The kernel of co-HLEX is a hierarchical recursive concurrent theorem prover nicknamed HRCTL. Due to its recursive nature, HRCTL has a size of only O(1,000) lines in KL1; the kernel language of ICOT. Due to its stream-parallel and distributed-memory architecture, nearly linear time complexity could be attained. Moreover, shape and wire abutment among modules running in parallel could be made through message passing cooperations. In this paper, a brief overview of co-HLEX is given with its application to bipolar-analog LSI layout." Fifth generation computers Komatsu, Keiko Verfasser aut Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 707 (DE-604)BV010923438 707 |
| spellingShingle | Watanabe, Tosahinori Komatsu, Keiko Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report Fifth generation computers |
| title | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine |
| title_auth | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine |
| title_exact_search | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine |
| title_full | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine by T. Watanabe & K. Komatsu |
| title_fullStr | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine by T. Watanabe & K. Komatsu |
| title_full_unstemmed | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine by T. Watanabe & K. Komatsu |
| title_short | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine |
| title_sort | co hlex lsi layout system on japan s fifth generation parallel inference machine |
| topic | Fifth generation computers |
| topic_facet | Fifth generation computers |
| volume_link | (DE-604)BV010923438 |
| work_keys_str_mv | AT watanabetosahinori cohlexlsilayoutsystemonjapansfifthgenerationparallelinferencemachine AT komatsukeiko cohlexlsilayoutsystemonjapansfifthgenerationparallelinferencemachine |