Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine:
Abstract: "Co-HLEX is a cooperative hierarchical layout problem solver developed as an application program of parallel inference machines; Multi-PSI and PIM. The kernel of co-HLEX is a hierarchical recursive concurrent theorem prover nicknamed HRCTL. Due to its recursive nature, HRCTL has a siz...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Tokyo, Japan
1991
|
| Schriftenreihe: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
707 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "Co-HLEX is a cooperative hierarchical layout problem solver developed as an application program of parallel inference machines; Multi-PSI and PIM. The kernel of co-HLEX is a hierarchical recursive concurrent theorem prover nicknamed HRCTL. Due to its recursive nature, HRCTL has a size of only O(1,000) lines in KL1; the kernel language of ICOT. Due to its stream-parallel and distributed-memory architecture, nearly linear time complexity could be attained. Moreover, shape and wire abutment among modules running in parallel could be made through message passing cooperations. In this paper, a brief overview of co-HLEX is given with its application to bipolar-analog LSI layout." |
| Beschreibung: | 10 S. |
Internformat
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| 520 | 3 | |a Abstract: "Co-HLEX is a cooperative hierarchical layout problem solver developed as an application program of parallel inference machines; Multi-PSI and PIM. The kernel of co-HLEX is a hierarchical recursive concurrent theorem prover nicknamed HRCTL. Due to its recursive nature, HRCTL has a size of only O(1,000) lines in KL1; the kernel language of ICOT. Due to its stream-parallel and distributed-memory architecture, nearly linear time complexity could be attained. Moreover, shape and wire abutment among modules running in parallel could be made through message passing cooperations. In this paper, a brief overview of co-HLEX is given with its application to bipolar-analog LSI layout." | |
| 650 | 4 | |a Fifth generation computers | |
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Datensatz im Suchindex
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| author | Watanabe, Tosahinori Komatsu, Keiko |
| author_facet | Watanabe, Tosahinori Komatsu, Keiko |
| author_role | aut aut |
| author_sort | Watanabe, Tosahinori |
| author_variant | t w tw k k kk |
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| bvnumber | BV010956036 |
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| id | DE-604.BV010956036 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:01:38Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007328218 |
| oclc_num | 26483682 |
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| physical | 10 S. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| spelling | Watanabe, Tosahinori Verfasser aut Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine by T. Watanabe & K. Komatsu Tokyo, Japan 1991 10 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 707 Abstract: "Co-HLEX is a cooperative hierarchical layout problem solver developed as an application program of parallel inference machines; Multi-PSI and PIM. The kernel of co-HLEX is a hierarchical recursive concurrent theorem prover nicknamed HRCTL. Due to its recursive nature, HRCTL has a size of only O(1,000) lines in KL1; the kernel language of ICOT. Due to its stream-parallel and distributed-memory architecture, nearly linear time complexity could be attained. Moreover, shape and wire abutment among modules running in parallel could be made through message passing cooperations. In this paper, a brief overview of co-HLEX is given with its application to bipolar-analog LSI layout." Fifth generation computers Komatsu, Keiko Verfasser aut Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 707 (DE-604)BV010923438 707 |
| spellingShingle | Watanabe, Tosahinori Komatsu, Keiko Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report Fifth generation computers |
| title | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine |
| title_auth | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine |
| title_exact_search | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine |
| title_full | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine by T. Watanabe & K. Komatsu |
| title_fullStr | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine by T. Watanabe & K. Komatsu |
| title_full_unstemmed | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine by T. Watanabe & K. Komatsu |
| title_short | Co-HLEX, LSI layout system on Japan's Fifth Generation parallel inference machine |
| title_sort | co hlex lsi layout system on japan s fifth generation parallel inference machine |
| topic | Fifth generation computers |
| topic_facet | Fifth generation computers |
| volume_link | (DE-604)BV010923438 |
| work_keys_str_mv | AT watanabetosahinori cohlexlsilayoutsystemonjapansfifthgenerationparallelinferencemachine AT komatsukeiko cohlexlsilayoutsystemonjapansfifthgenerationparallelinferencemachine |