Processor element architecture for parallel inference machine: PIM p:
Abstract: "This paper describes the design of processor element architecture for the parallel inference machine prototype, PIM/p. Several innovative features are incorporated in the processor architecture to suit concurrent logic programming languages such as KL1. The processor's design is...
Gespeichert in:
| Format: | Buch |
|---|---|
| Sprache: | Japanese English |
| Veröffentlicht: |
Tokyo, Japan
1990
|
| Schriftenreihe: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
577 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "This paper describes the design of processor element architecture for the parallel inference machine prototype, PIM/p. Several innovative features are incorporated in the processor architecture to suit concurrent logic programming languages such as KL1. The processor's design is based on tagged architecture. With the variety of tag handling operations, instructions can be executed by one cycle pitch pipeline. Macro-call instructions are introduced to enable a lightweight subroutine call function for polymorphic operations required in execution of high level languages such as logic programming languages. This enables system designers to easily define high level instructions without losing the benefits of the pipelining mechanism Dedicated instructions are introduced to support incremental garbage collection. Local coherent cache and optimized memory operations tailored to the memory access characteristics of KL1 can reduce common bus traffic in shared memory multiprocessors. In this paper, we describe the design decisions for these architecture features. The LSIs are now being fabricated using CMOS standard cell technology. |
| Beschreibung: | 26 S. |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV010949953 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 960916s1990 |||| 00||| jpnod | ||
| 035 | |a (OCoLC)26737749 | ||
| 035 | |a (DE-599)BVBBV010949953 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a jpn |a eng | |
| 049 | |a DE-91G | ||
| 245 | 1 | 0 | |a Processor element architecture for parallel inference machine: PIM p |c by A. Goto ... |
| 264 | 1 | |a Tokyo, Japan |c 1990 | |
| 300 | |a 26 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 577 | |
| 520 | 3 | |a Abstract: "This paper describes the design of processor element architecture for the parallel inference machine prototype, PIM/p. Several innovative features are incorporated in the processor architecture to suit concurrent logic programming languages such as KL1. The processor's design is based on tagged architecture. With the variety of tag handling operations, instructions can be executed by one cycle pitch pipeline. Macro-call instructions are introduced to enable a lightweight subroutine call function for polymorphic operations required in execution of high level languages such as logic programming languages. This enables system designers to easily define high level instructions without losing the benefits of the pipelining mechanism | |
| 520 | 3 | |a Dedicated instructions are introduced to support incremental garbage collection. Local coherent cache and optimized memory operations tailored to the memory access characteristics of KL1 can reduce common bus traffic in shared memory multiprocessors. In this paper, we describe the design decisions for these architecture features. The LSIs are now being fabricated using CMOS standard cell technology. | |
| 650 | 4 | |a KL1 (Computer program language) | |
| 650 | 4 | |a Logic programming | |
| 650 | 4 | |a Parallel programming (Electronic computers) | |
| 700 | 1 | |a Goto, Atsuhiro |e Sonstige |4 oth | |
| 830 | 0 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 577 |w (DE-604)BV010923438 |9 577 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-007323807 | ||
Datensatz im Suchindex
| _version_ | 1804125437093216256 |
|---|---|
| any_adam_object | |
| building | Verbundindex |
| bvnumber | BV010949953 |
| ctrlnum | (OCoLC)26737749 (DE-599)BVBBV010949953 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02216nam a2200325 cb4500</leader><controlfield tag="001">BV010949953</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">960916s1990 |||| 00||| jpnod</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)26737749</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV010949953</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">jpn</subfield><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Processor element architecture for parallel inference machine: PIM p</subfield><subfield code="c">by A. Goto ...</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Tokyo, Japan</subfield><subfield code="c">1990</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">26 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">577</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Abstract: "This paper describes the design of processor element architecture for the parallel inference machine prototype, PIM/p. Several innovative features are incorporated in the processor architecture to suit concurrent logic programming languages such as KL1. The processor's design is based on tagged architecture. With the variety of tag handling operations, instructions can be executed by one cycle pitch pipeline. Macro-call instructions are introduced to enable a lightweight subroutine call function for polymorphic operations required in execution of high level languages such as logic programming languages. This enables system designers to easily define high level instructions without losing the benefits of the pipelining mechanism</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Dedicated instructions are introduced to support incremental garbage collection. Local coherent cache and optimized memory operations tailored to the memory access characteristics of KL1 can reduce common bus traffic in shared memory multiprocessors. In this paper, we describe the design decisions for these architecture features. The LSIs are now being fabricated using CMOS standard cell technology.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">KL1 (Computer program language)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic programming</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Parallel programming (Electronic computers)</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Goto, Atsuhiro</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">577</subfield><subfield code="w">(DE-604)BV010923438</subfield><subfield code="9">577</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-007323807</subfield></datafield></record></collection> |
| id | DE-604.BV010949953 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:01:32Z |
| institution | BVB |
| language | Japanese English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007323807 |
| oclc_num | 26737749 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 26 S. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| spelling | Processor element architecture for parallel inference machine: PIM p by A. Goto ... Tokyo, Japan 1990 26 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 577 Abstract: "This paper describes the design of processor element architecture for the parallel inference machine prototype, PIM/p. Several innovative features are incorporated in the processor architecture to suit concurrent logic programming languages such as KL1. The processor's design is based on tagged architecture. With the variety of tag handling operations, instructions can be executed by one cycle pitch pipeline. Macro-call instructions are introduced to enable a lightweight subroutine call function for polymorphic operations required in execution of high level languages such as logic programming languages. This enables system designers to easily define high level instructions without losing the benefits of the pipelining mechanism Dedicated instructions are introduced to support incremental garbage collection. Local coherent cache and optimized memory operations tailored to the memory access characteristics of KL1 can reduce common bus traffic in shared memory multiprocessors. In this paper, we describe the design decisions for these architecture features. The LSIs are now being fabricated using CMOS standard cell technology. KL1 (Computer program language) Logic programming Parallel programming (Electronic computers) Goto, Atsuhiro Sonstige oth Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 577 (DE-604)BV010923438 577 |
| spellingShingle | Processor element architecture for parallel inference machine: PIM p Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report KL1 (Computer program language) Logic programming Parallel programming (Electronic computers) |
| title | Processor element architecture for parallel inference machine: PIM p |
| title_auth | Processor element architecture for parallel inference machine: PIM p |
| title_exact_search | Processor element architecture for parallel inference machine: PIM p |
| title_full | Processor element architecture for parallel inference machine: PIM p by A. Goto ... |
| title_fullStr | Processor element architecture for parallel inference machine: PIM p by A. Goto ... |
| title_full_unstemmed | Processor element architecture for parallel inference machine: PIM p by A. Goto ... |
| title_short | Processor element architecture for parallel inference machine: PIM p |
| title_sort | processor element architecture for parallel inference machine pim p |
| topic | KL1 (Computer program language) Logic programming Parallel programming (Electronic computers) |
| topic_facet | KL1 (Computer program language) Logic programming Parallel programming (Electronic computers) |
| volume_link | (DE-604)BV010923438 |
| work_keys_str_mv | AT gotoatsuhiro processorelementarchitectureforparallelinferencemachinepimp |