A cooperative logic design expert system on a multiprocessor:
Abstract: "CAD systems that can quickly produce quality designs are needed for the expanding VLSI market. This paper presents a cooperative design mechanism in a cooperative logic design expert system on a multiprocessor, co-LODEX. co-LODEX accepts constraints on area and speed, and outputs a C...
Gespeichert in:
| Format: | Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Tokyo, Japan
1990
|
| Schriftenreihe: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
567 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "CAD systems that can quickly produce quality designs are needed for the expanding VLSI market. This paper presents a cooperative design mechanism in a cooperative logic design expert system on a multiprocessor, co-LODEX. co-LODEX accepts constraints on area and speed, and outputs a CMOS standard cell netlist that satisfies the constraints. Short turnaround is expected through the combination of parallel processing by several processors and their cooperation. The cooperative design mechanism is based on an evaluation-redesign mechanism using assumption-based reasoning within a single processor. Design alternatives are considered as assumptions and constraint violations as contradictions Redesign is implemented as contradiction resolution. The evaluate-redesign cycle repeats itself until the design satisfies the specified constraints. co-LODEX divides the whole circuit to be designed into subcircuits in advance and designs each subcircuit on each processor to take advantage of parallel processing. Global evaluation-redesign takes place by processors exchanging design results in terms of gate counts and delays (in case of success) or justifications for constraint violations (in case of failure) Experimental results on the cooperative design algorithm suggest that the number of iterations is considerably reduced. It is observed that the number of iterations through cooperation is less than half that for the sequential evaluation-redesign algorithm. |
| Beschreibung: | 15, [6] S. graph. Darst. |
Internformat
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| 245 | 1 | 0 | |a A cooperative logic design expert system on a multiprocessor |c by Y. Minoda ... |
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| 490 | 1 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 567 | |
| 520 | 3 | |a Abstract: "CAD systems that can quickly produce quality designs are needed for the expanding VLSI market. This paper presents a cooperative design mechanism in a cooperative logic design expert system on a multiprocessor, co-LODEX. co-LODEX accepts constraints on area and speed, and outputs a CMOS standard cell netlist that satisfies the constraints. Short turnaround is expected through the combination of parallel processing by several processors and their cooperation. The cooperative design mechanism is based on an evaluation-redesign mechanism using assumption-based reasoning within a single processor. Design alternatives are considered as assumptions and constraint violations as contradictions | |
| 520 | 3 | |a Redesign is implemented as contradiction resolution. The evaluate-redesign cycle repeats itself until the design satisfies the specified constraints. co-LODEX divides the whole circuit to be designed into subcircuits in advance and designs each subcircuit on each processor to take advantage of parallel processing. Global evaluation-redesign takes place by processors exchanging design results in terms of gate counts and delays (in case of success) or justifications for constraint violations (in case of failure) | |
| 520 | 3 | |a Experimental results on the cooperative design algorithm suggest that the number of iterations is considerably reduced. It is observed that the number of iterations through cooperation is less than half that for the sequential evaluation-redesign algorithm. | |
| 650 | 4 | |a Expert systems (Computer science) | |
| 650 | 4 | |a Logic, Symbolic and mathematical | |
| 650 | 4 | |a Multiprocessors | |
| 650 | 4 | |a Reasoning | |
| 700 | 1 | |a Minoda, Yoriko |e Sonstige |4 oth | |
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| id | DE-604.BV010949790 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:01:32Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007323664 |
| oclc_num | 24838870 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 15, [6] S. graph. Darst. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| spelling | A cooperative logic design expert system on a multiprocessor by Y. Minoda ... Tokyo, Japan 1990 15, [6] S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 567 Abstract: "CAD systems that can quickly produce quality designs are needed for the expanding VLSI market. This paper presents a cooperative design mechanism in a cooperative logic design expert system on a multiprocessor, co-LODEX. co-LODEX accepts constraints on area and speed, and outputs a CMOS standard cell netlist that satisfies the constraints. Short turnaround is expected through the combination of parallel processing by several processors and their cooperation. The cooperative design mechanism is based on an evaluation-redesign mechanism using assumption-based reasoning within a single processor. Design alternatives are considered as assumptions and constraint violations as contradictions Redesign is implemented as contradiction resolution. The evaluate-redesign cycle repeats itself until the design satisfies the specified constraints. co-LODEX divides the whole circuit to be designed into subcircuits in advance and designs each subcircuit on each processor to take advantage of parallel processing. Global evaluation-redesign takes place by processors exchanging design results in terms of gate counts and delays (in case of success) or justifications for constraint violations (in case of failure) Experimental results on the cooperative design algorithm suggest that the number of iterations is considerably reduced. It is observed that the number of iterations through cooperation is less than half that for the sequential evaluation-redesign algorithm. Expert systems (Computer science) Logic, Symbolic and mathematical Multiprocessors Reasoning Minoda, Yoriko Sonstige oth Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 567 (DE-604)BV010923438 567 |
| spellingShingle | A cooperative logic design expert system on a multiprocessor Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report Expert systems (Computer science) Logic, Symbolic and mathematical Multiprocessors Reasoning |
| title | A cooperative logic design expert system on a multiprocessor |
| title_auth | A cooperative logic design expert system on a multiprocessor |
| title_exact_search | A cooperative logic design expert system on a multiprocessor |
| title_full | A cooperative logic design expert system on a multiprocessor by Y. Minoda ... |
| title_fullStr | A cooperative logic design expert system on a multiprocessor by Y. Minoda ... |
| title_full_unstemmed | A cooperative logic design expert system on a multiprocessor by Y. Minoda ... |
| title_short | A cooperative logic design expert system on a multiprocessor |
| title_sort | a cooperative logic design expert system on a multiprocessor |
| topic | Expert systems (Computer science) Logic, Symbolic and mathematical Multiprocessors Reasoning |
| topic_facet | Expert systems (Computer science) Logic, Symbolic and mathematical Multiprocessors Reasoning |
| volume_link | (DE-604)BV010923438 |
| work_keys_str_mv | AT minodayoriko acooperativelogicdesignexpertsystemonamultiprocessor |