Design and performance of a coherent cache for parallel logic programming architectures:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Tokyo, Japan
1988
|
| Schriftenreihe: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
436 |
| Schlagworte: | |
| Beschreibung: | 21 S. |
Internformat
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| 100 | 1 | |a Goto, Atsuhiro |e Verfasser |4 aut | |
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| 650 | 4 | |a Cache memory | |
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| 650 | 4 | |a Parallel programming (Computer science) | |
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| 700 | 1 | |a Tich, Evan |e Verfasser |4 aut | |
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Datensatz im Suchindex
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| author | Goto, Atsuhiro Matsumoto, Akira Tich, Evan |
| author_facet | Goto, Atsuhiro Matsumoto, Akira Tich, Evan |
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| id | DE-604.BV010946834 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:01:29Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007321092 |
| oclc_num | 20515172 |
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| physical | 21 S. |
| publishDate | 1988 |
| publishDateSearch | 1988 |
| publishDateSort | 1988 |
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| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| spelling | Goto, Atsuhiro Verfasser aut Design and performance of a coherent cache for parallel logic programming architectures by A. Goto, A. Matsumoto and E. Tich Tokyo, Japan 1988 21 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 436 Cache memory Logic programming Parallel programming (Computer science) Matsumoto, Akira Verfasser aut Tich, Evan Verfasser aut Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 436 (DE-604)BV010923438 436 |
| spellingShingle | Goto, Atsuhiro Matsumoto, Akira Tich, Evan Design and performance of a coherent cache for parallel logic programming architectures Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report Cache memory Logic programming Parallel programming (Computer science) |
| title | Design and performance of a coherent cache for parallel logic programming architectures |
| title_auth | Design and performance of a coherent cache for parallel logic programming architectures |
| title_exact_search | Design and performance of a coherent cache for parallel logic programming architectures |
| title_full | Design and performance of a coherent cache for parallel logic programming architectures by A. Goto, A. Matsumoto and E. Tich |
| title_fullStr | Design and performance of a coherent cache for parallel logic programming architectures by A. Goto, A. Matsumoto and E. Tich |
| title_full_unstemmed | Design and performance of a coherent cache for parallel logic programming architectures by A. Goto, A. Matsumoto and E. Tich |
| title_short | Design and performance of a coherent cache for parallel logic programming architectures |
| title_sort | design and performance of a coherent cache for parallel logic programming architectures |
| topic | Cache memory Logic programming Parallel programming (Computer science) |
| topic_facet | Cache memory Logic programming Parallel programming (Computer science) |
| volume_link | (DE-604)BV010923438 |
| work_keys_str_mv | AT gotoatsuhiro designandperformanceofacoherentcacheforparallellogicprogrammingarchitectures AT matsumotoakira designandperformanceofacoherentcacheforparallellogicprogrammingarchitectures AT tichevan designandperformanceofacoherentcacheforparallellogicprogrammingarchitectures |