Verification of systolic arrays in M2L(Str):
Abstract: "VLSI designs often show regular structures, where issues like temporal and spatial recursivity, and bidirectionality play a central role. This document introduces the modelling of a class of regular VLSI circuits, namely iterative systolic arrays, in a particular second- order logic,...
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Passau
1996
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| Schriftenreihe: | Universität <Passau> / Fakultät für Mathematik und Informatik: MIP
1996,13 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "VLSI designs often show regular structures, where issues like temporal and spatial recursivity, and bidirectionality play a central role. This document introduces the modelling of a class of regular VLSI circuits, namely iterative systolic arrays, in a particular second- order logic, and presents fully automatic verification of pipeline properties for an example from the literature." |
| Beschreibung: | 29, 4 S. graph. Darst. |
Internformat
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| 520 | 3 | |a Abstract: "VLSI designs often show regular structures, where issues like temporal and spatial recursivity, and bidirectionality play a central role. This document introduces the modelling of a class of regular VLSI circuits, namely iterative systolic arrays, in a particular second- order logic, and presents fully automatic verification of pipeline properties for an example from the literature." | |
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| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Mathematical models | |
| 650 | 4 | |a Systolic array circuits |x Mathematical models | |
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Datensatz im Suchindex
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| id | DE-604.BV010907983 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:00:57Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007296242 |
| oclc_num | 38179130 |
| open_access_boolean | |
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| owner_facet | DE-154 DE-739 DE-12 DE-91G DE-BY-TUM DE-384 DE-634 |
| physical | 29, 4 S. graph. Darst. |
| publishDate | 1996 |
| publishDateSearch | 1996 |
| publishDateSort | 1996 |
| record_format | marc |
| series2 | Universität <Passau> / Fakultät für Mathematik und Informatik: MIP |
| spelling | Margaria, Tiziana Verfasser aut Verification of systolic arrays in M2L(Str) Tiziana Margaria Passau 1996 29, 4 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Universität <Passau> / Fakultät für Mathematik und Informatik: MIP 1996,13 Abstract: "VLSI designs often show regular structures, where issues like temporal and spatial recursivity, and bidirectionality play a central role. This document introduces the modelling of a class of regular VLSI circuits, namely iterative systolic arrays, in a particular second- order logic, and presents fully automatic verification of pipeline properties for an example from the literature." Mathematisches Modell Integrated circuits Verification Integrated circuits Very large scale integration Mathematical models Systolic array circuits Mathematical models Mathematik (DE-588)4037944-9 gnd rswk-swf Theoretische Informatik (DE-588)4196735-5 gnd rswk-swf Informatik (DE-588)4026894-9 gnd rswk-swf Theoretische Informatik (DE-588)4196735-5 s Informatik (DE-588)4026894-9 s Mathematik (DE-588)4037944-9 s DE-604 Fakultät für Mathematik und Informatik: MIP Universität <Passau> 1996,13 (DE-604)BV000905393 1996,13 |
| spellingShingle | Margaria, Tiziana Verification of systolic arrays in M2L(Str) Mathematisches Modell Integrated circuits Verification Integrated circuits Very large scale integration Mathematical models Systolic array circuits Mathematical models Mathematik (DE-588)4037944-9 gnd Theoretische Informatik (DE-588)4196735-5 gnd Informatik (DE-588)4026894-9 gnd |
| subject_GND | (DE-588)4037944-9 (DE-588)4196735-5 (DE-588)4026894-9 |
| title | Verification of systolic arrays in M2L(Str) |
| title_auth | Verification of systolic arrays in M2L(Str) |
| title_exact_search | Verification of systolic arrays in M2L(Str) |
| title_full | Verification of systolic arrays in M2L(Str) Tiziana Margaria |
| title_fullStr | Verification of systolic arrays in M2L(Str) Tiziana Margaria |
| title_full_unstemmed | Verification of systolic arrays in M2L(Str) Tiziana Margaria |
| title_short | Verification of systolic arrays in M2L(Str) |
| title_sort | verification of systolic arrays in m2l str |
| topic | Mathematisches Modell Integrated circuits Verification Integrated circuits Very large scale integration Mathematical models Systolic array circuits Mathematical models Mathematik (DE-588)4037944-9 gnd Theoretische Informatik (DE-588)4196735-5 gnd Informatik (DE-588)4026894-9 gnd |
| topic_facet | Mathematisches Modell Integrated circuits Verification Integrated circuits Very large scale integration Mathematical models Systolic array circuits Mathematical models Mathematik Theoretische Informatik Informatik |
| volume_link | (DE-604)BV000905393 |
| work_keys_str_mv | AT margariatiziana verificationofsystolicarraysinm2lstr |