Logic synthesis for field programmable gate arrays:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston u.a.
Kluwer
1995
|
| Schriftenreihe: | The Kluwer international series in engineering and computer science
324 |
| Schlagworte: | |
| Beschreibung: | XV, 427 S. graph. Darst. |
| ISBN: | 0792395964 |
Internformat
MARC
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| 035 | |a (OCoLC)32589357 | ||
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| 041 | 0 | |a eng | |
| 049 | |a DE-91G |a DE-91 | ||
| 050 | 0 | |a TK7895.G36 | |
| 082 | 0 | |a 621.39/5 |2 20 | |
| 084 | |a DAT 195f |2 stub | ||
| 100 | 1 | |a Murgai, Rajeev |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Logic synthesis for field programmable gate arrays |c by Rajeev Murgai ; Robert K. Brayton ; Alberto Sangiovanni-Vincentelli |
| 246 | 1 | 3 | |a Logic synthesis for field-programmable gate arrays |
| 264 | 1 | |a Boston u.a. |b Kluwer |c 1995 | |
| 300 | |a XV, 427 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a The Kluwer international series in engineering and computer science |v 324 | |
| 650 | 7 | |a Circuits intégrés - Conception et construction |2 ram | |
| 650 | 7 | |a Réseaux logiques programmables |2 ram | |
| 650 | 4 | |a Field programmable gate arrays | |
| 650 | 4 | |a Programmable array logic | |
| 700 | 1 | |a Brayton, Robert K. |e Verfasser |4 aut | |
| 700 | 1 | |a Sangiovanni-Vincentelli, Alberto |e Verfasser |4 aut | |
| 830 | 0 | |a The Kluwer international series in engineering and computer science |v 324 |w (DE-604)BV023545171 |9 324 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-007034763 | ||
Datensatz im Suchindex
| _version_ | 1804125021653696512 |
|---|---|
| any_adam_object | |
| author | Murgai, Rajeev Brayton, Robert K. Sangiovanni-Vincentelli, Alberto |
| author_facet | Murgai, Rajeev Brayton, Robert K. Sangiovanni-Vincentelli, Alberto |
| author_role | aut aut aut |
| author_sort | Murgai, Rajeev |
| author_variant | r m rm r k b rk rkb a s v asv |
| building | Verbundindex |
| bvnumber | BV010552788 |
| callnumber-first | T - Technology |
| callnumber-label | TK7895 |
| callnumber-raw | TK7895.G36 |
| callnumber-search | TK7895.G36 |
| callnumber-sort | TK 47895 G36 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_tum | DAT 195f |
| ctrlnum | (OCoLC)32589357 (DE-599)BVBBV010552788 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV010552788 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T17:54:56Z |
| institution | BVB |
| isbn | 0792395964 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007034763 |
| oclc_num | 32589357 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-91 DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM DE-91 DE-BY-TUM |
| physical | XV, 427 S. graph. Darst. |
| publishDate | 1995 |
| publishDateSearch | 1995 |
| publishDateSort | 1995 |
| publisher | Kluwer |
| record_format | marc |
| series | The Kluwer international series in engineering and computer science |
| series2 | The Kluwer international series in engineering and computer science |
| spelling | Murgai, Rajeev Verfasser aut Logic synthesis for field programmable gate arrays by Rajeev Murgai ; Robert K. Brayton ; Alberto Sangiovanni-Vincentelli Logic synthesis for field-programmable gate arrays Boston u.a. Kluwer 1995 XV, 427 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier The Kluwer international series in engineering and computer science 324 Circuits intégrés - Conception et construction ram Réseaux logiques programmables ram Field programmable gate arrays Programmable array logic Brayton, Robert K. Verfasser aut Sangiovanni-Vincentelli, Alberto Verfasser aut The Kluwer international series in engineering and computer science 324 (DE-604)BV023545171 324 |
| spellingShingle | Murgai, Rajeev Brayton, Robert K. Sangiovanni-Vincentelli, Alberto Logic synthesis for field programmable gate arrays The Kluwer international series in engineering and computer science Circuits intégrés - Conception et construction ram Réseaux logiques programmables ram Field programmable gate arrays Programmable array logic |
| title | Logic synthesis for field programmable gate arrays |
| title_alt | Logic synthesis for field-programmable gate arrays |
| title_auth | Logic synthesis for field programmable gate arrays |
| title_exact_search | Logic synthesis for field programmable gate arrays |
| title_full | Logic synthesis for field programmable gate arrays by Rajeev Murgai ; Robert K. Brayton ; Alberto Sangiovanni-Vincentelli |
| title_fullStr | Logic synthesis for field programmable gate arrays by Rajeev Murgai ; Robert K. Brayton ; Alberto Sangiovanni-Vincentelli |
| title_full_unstemmed | Logic synthesis for field programmable gate arrays by Rajeev Murgai ; Robert K. Brayton ; Alberto Sangiovanni-Vincentelli |
| title_short | Logic synthesis for field programmable gate arrays |
| title_sort | logic synthesis for field programmable gate arrays |
| topic | Circuits intégrés - Conception et construction ram Réseaux logiques programmables ram Field programmable gate arrays Programmable array logic |
| topic_facet | Circuits intégrés - Conception et construction Réseaux logiques programmables Field programmable gate arrays Programmable array logic |
| volume_link | (DE-604)BV023545171 |
| work_keys_str_mv | AT murgairajeev logicsynthesisforfieldprogrammablegatearrays AT braytonrobertk logicsynthesisforfieldprogrammablegatearrays AT sangiovannivincentellialberto logicsynthesisforfieldprogrammablegatearrays |