Verfügbarkeit: Algorithms for VLSI physical design automation

Algorithms for VLSI physical design automation:

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Bibliographische Detailangaben
1. Verfasser:	Sherwani, Naveed A. (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	Boston u.a. Kluwer 1995
Ausgabe:	2. ed.
Schlagworte:	Circuits intégreés à très grande échelle - conception et construction DESSIN AUTOMATIQUE algorithme VLSI Algorithms Integrated circuits > Very large scale integration > Computer-aided design VLSI Schaltungsentwurf Entwurf Algorithmus
Beschreibung:	XXV, 538 S. Ill., graph. Darst.
ISBN:	0792395921

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MARC


LEADER	00000nam a2200000 c 4500
001	BV010536578
003	DE-604
005	00000000000000.0
007	t
008	951221s1995 ad\|\| \|\|\|\| 00\|\|\| eng d
020			\|a 0792395921 \|9 0-7923-9592-1
035			\|a (OCoLC)32394480
035			\|a (DE-599)BVBBV010536578
040			\|a DE-604 \|b ger \|e rakddb
041	0		\|a eng
049			\|a DE-91G
050		0	\|a TK7874
082	0		\|a 621.39/5 \|2 20
084			\|a ST 190 \|0 (DE-625)143607: \|2 rvk
084			\|a ELT 272f \|2 stub
100	1		\|a Sherwani, Naveed A. \|e Verfasser \|4 aut
245	1	0	\|a Algorithms for VLSI physical design automation \|c Naveed Sherwani
250			\|a 2. ed.
264		1	\|a Boston u.a. \|b Kluwer \|c 1995
300			\|a XXV, 538 S. \|b Ill., graph. Darst.
336			\|b txt \|2 rdacontent
337			\|b n \|2 rdamedia
338			\|b nc \|2 rdacarrier
650		7	\|a Circuits intégreés à très grande échelle - conception et construction \|2 ram
650		7	\|a DESSIN AUTOMATIQUE \|2 inriac
650		7	\|a algorithme VLSI \|2 inriac
650		4	\|a Algorithms
650		4	\|a Integrated circuits \|x Very large scale integration \|x Computer-aided design
650	0	7	\|a VLSI \|0 (DE-588)4117388-0 \|2 gnd \|9 rswk-swf
650	0	7	\|a Schaltungsentwurf \|0 (DE-588)4179389-4 \|2 gnd \|9 rswk-swf
650	0	7	\|a Entwurf \|0 (DE-588)4121208-3 \|2 gnd \|9 rswk-swf
650	0	7	\|a Algorithmus \|0 (DE-588)4001183-5 \|2 gnd \|9 rswk-swf
689	0	0	\|a VLSI \|0 (DE-588)4117388-0 \|D s
689	0	1	\|a Entwurf \|0 (DE-588)4121208-3 \|D s
689	0		\|5 DE-604
689	1	0	\|a VLSI \|0 (DE-588)4117388-0 \|D s
689	1	1	\|a Algorithmus \|0 (DE-588)4001183-5 \|D s
689	1		\|8 1\p \|5 DE-604
689	2	0	\|a VLSI \|0 (DE-588)4117388-0 \|D s
689	2	1	\|a Schaltungsentwurf \|0 (DE-588)4179389-4 \|D s
689	2		\|8 2\p \|5 DE-604
999			\|a oai:aleph.bib-bvb.de:BVB01-007023706
883	1		\|8 1\p \|a cgwrk \|d 20201028 \|q DE-101 \|u https://d-nb.info/provenance/plan#cgwrk
883	1		\|8 2\p \|a cgwrk \|d 20201028 \|q DE-101 \|u https://d-nb.info/provenance/plan#cgwrk

Datensatz im Suchindex

_version_	1804125005501431808
any_adam_object
author	Sherwani, Naveed A.
author_facet	Sherwani, Naveed A.
author_role	aut
author_sort	Sherwani, Naveed A.
author_variant	n a s na nas
building	Verbundindex
bvnumber	BV010536578
callnumber-first	T - Technology
callnumber-label	TK7874
callnumber-raw	TK7874
callnumber-search	TK7874
callnumber-sort	TK 47874
callnumber-subject	TK - Electrical and Nuclear Engineering
classification_rvk	ST 190
classification_tum	ELT 272f
ctrlnum	(OCoLC)32394480 (DE-599)BVBBV010536578
dewey-full	621.39/5
dewey-hundreds	600 - Technology (Applied sciences)
dewey-ones	621 - Applied physics
dewey-raw	621.39/5
dewey-search	621.39/5
dewey-sort	3621.39 15
dewey-tens	620 - Engineering and allied operations
discipline	Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik
edition	2. ed.
format	Book
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01945nam a2200553 c 4500</leader><controlfield tag="001">BV010536578</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">951221s1995 ad\|\| \|\|\|\| 00\|\|\| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0792395921</subfield><subfield code="9">0-7923-9592-1</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)32394480</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV010536578</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7874</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield><subfield code="2">20</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 190</subfield><subfield code="0">(DE-625)143607:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 272f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Sherwani, Naveed A.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Algorithms for VLSI physical design automation</subfield><subfield code="c">Naveed Sherwani</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">2. ed.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston u.a.</subfield><subfield code="b">Kluwer</subfield><subfield code="c">1995</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXV, 538 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Circuits intégreés à très grande échelle - conception et construction</subfield><subfield code="2">ram</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">DESSIN AUTOMATIQUE</subfield><subfield code="2">inriac</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">algorithme VLSI</subfield><subfield code="2">inriac</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Algorithms</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Computer-aided design</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Algorithmus</subfield><subfield code="0">(DE-588)4001183-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Algorithmus</subfield><subfield code="0">(DE-588)4001183-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2="1"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-007023706</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield></record></collection>
id	DE-604.BV010536578
illustrated	Illustrated
indexdate	2024-07-09T17:54:41Z
institution	BVB
isbn	0792395921
language	English
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-007023706
oclc_num	32394480
open_access_boolean
owner	DE-91G DE-BY-TUM
owner_facet	DE-91G DE-BY-TUM
physical	XXV, 538 S. Ill., graph. Darst.
publishDate	1995
publishDateSearch	1995
publishDateSort	1995
publisher	Kluwer
record_format	marc
spelling	Sherwani, Naveed A. Verfasser aut Algorithms for VLSI physical design automation Naveed Sherwani 2. ed. Boston u.a. Kluwer 1995 XXV, 538 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Circuits intégreés à très grande échelle - conception et construction ram DESSIN AUTOMATIQUE inriac algorithme VLSI inriac Algorithms Integrated circuits Very large scale integration Computer-aided design VLSI (DE-588)4117388-0 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Algorithmus (DE-588)4001183-5 gnd rswk-swf VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s DE-604 Algorithmus (DE-588)4001183-5 s 1\p DE-604 Schaltungsentwurf (DE-588)4179389-4 s 2\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk
spellingShingle	Sherwani, Naveed A. Algorithms for VLSI physical design automation Circuits intégreés à très grande échelle - conception et construction ram DESSIN AUTOMATIQUE inriac algorithme VLSI inriac Algorithms Integrated circuits Very large scale integration Computer-aided design VLSI (DE-588)4117388-0 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Entwurf (DE-588)4121208-3 gnd Algorithmus (DE-588)4001183-5 gnd
subject_GND	(DE-588)4117388-0 (DE-588)4179389-4 (DE-588)4121208-3 (DE-588)4001183-5
title	Algorithms for VLSI physical design automation
title_auth	Algorithms for VLSI physical design automation
title_exact_search	Algorithms for VLSI physical design automation
title_full	Algorithms for VLSI physical design automation Naveed Sherwani
title_fullStr	Algorithms for VLSI physical design automation Naveed Sherwani
title_full_unstemmed	Algorithms for VLSI physical design automation Naveed Sherwani
title_short	Algorithms for VLSI physical design automation
title_sort	algorithms for vlsi physical design automation
topic	Circuits intégreés à très grande échelle - conception et construction ram DESSIN AUTOMATIQUE inriac algorithme VLSI inriac Algorithms Integrated circuits Very large scale integration Computer-aided design VLSI (DE-588)4117388-0 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Entwurf (DE-588)4121208-3 gnd Algorithmus (DE-588)4001183-5 gnd
topic_facet	Circuits intégreés à très grande échelle - conception et construction DESSIN AUTOMATIQUE algorithme VLSI Algorithms Integrated circuits Very large scale integration Computer-aided design VLSI Schaltungsentwurf Entwurf Algorithmus
work_keys_str_mv	AT sherwaninaveeda algorithmsforvlsiphysicaldesignautomation

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