ISA system architecture:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Reading, Mass. u.a.
Addison-Wesley
1995
|
| Ausgabe: | 3. ed. |
| Schriftenreihe: | PC system architecture series
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXV, 515 S. graph. Darst. |
| ISBN: | 0201409968 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
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| 001 | BV010479488 | ||
| 003 | DE-604 | ||
| 005 | 20000407 | ||
| 007 | t | ||
| 008 | 951116s1995 d||| |||| 00||| engod | ||
| 020 | |a 0201409968 |9 0-201-40996-8 | ||
| 035 | |a (OCoLC)300364266 | ||
| 035 | |a (DE-599)BVBBV010479488 | ||
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| 041 | 0 | |a eng | |
| 049 | |a DE-91G |a DE-861 | ||
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| 100 | 1 | |a Shanley, Tom |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a ISA system architecture |c Tom Shanley and Don Anderson |
| 250 | |a 3. ed. | ||
| 264 | 1 | |a Reading, Mass. u.a. |b Addison-Wesley |c 1995 | |
| 300 | |a XXV, 515 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a PC system architecture series | |
| 650 | 4 | |a Architecture - Isa - Micro-Ordinateur - Microprocesseur - Ordinateur - Pc - Systeme | |
| 650 | 7 | |a Microordinateurs - Bus |2 ram | |
| 650 | 4 | |a Architektur | |
| 700 | 1 | |a Anderson, Don |e Verfasser |4 aut | |
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| 999 | |a oai:aleph.bib-bvb.de:BVB01-006982981 | ||
Datensatz im Suchindex
| _version_ | 1804124912418291712 |
|---|---|
| adam_text | ISA System
Architecture
Third Edition
MINDSHARE, INC
TOM SHANLEY
AND
DON ANDERSON
EDITED AND REVISED BY
JOHN SWINDLE
Addison-Wesley Publishing Company
Reading, Massachusetts • Menlo Park, California • New York
Don Mills, Ontario • Wokingham, England • Amsterdam
Bonn • Sydney • Singapore • Tokyo • Madrid • San Juan
Paris • Seoul • Milan • Mexico City • Taipei
Contents
Contents
Foreword xxiii
Acknowledgments xxv
About This Book
The MindShare Architecture Series 1
Organization of This Book 2
Who This Book Is For 2
Prerequisite Knowledge 2
Documentation Conventions 3
Hex Notation 3
Binary Notation 3
Decimal Notation 3
Signal Name Representation 3
Identification of Bit Fields (logical groups of bits or signals) 4
We Want Your Feedback 4
Overview
System Kernel 6
Memory Subsystems 6
ISA Subsystem 7
Origins of ISA 7
The IBM PC 7
The IBM PC/AT 8
The ISA Concept 8
Part 1: The System Kernel
Chapter 1: Intro to Microprocessor Communications
Instruction Fetch and Execution 11
General 11
In-Line Code Fetching 13
Reading and Writing 15
Type of Information Read from Memory : 16
Type of Information Written to Memory 16
The Buses 16
The Address Bus 17
Control Bus - Transaction Type and Synchronization 19
The Data Bus — Data Transfer Path 19
ISA System Architecture
Chapter 2: Introduction to the Bus Cycle
Introduction 21
Automatic Dishwasher - Classic State Machine Example 21
The System Clock - a Metronome 22
Microprocessor s Bus Cycle State Machine 23
Address Time 24
Data Time 25
The Wait State 26
Chapter 3: Addressing I/O and Memory
Evolution of Memory and I/O Address Space 29
Intel 8080 Microprocessor Address Space 29
8086 and 8088 Microprocessor Address Space 33
286 and 386SX Address Space 34
386DX, 486 and Pentium Processor Address Space 35
Memory Mapped I/O 36
The I/O Device 36
Chapter 4: The Address Decode Logic
The Address Decoder Concept 39
Data Bus Contention (Address Conflicts) 41
How Address Decoders Work 41
Example 1- PC and PC/XT ROM Address Decoder 42
Background 42
The PC/XT ROM Address Decode Logic 44
Example 2 - System Board I/O Address Decoder 47
Chapter 5: The 80286 Microprocessor
The 80286 Functional Units 53
The Instruction Unit 55
The Execution Unit 55
General Registers 56
The Status and Control Registers 59
The Address Unit 63
The Segment Registers 63
Segment Register Usage in Real Mode 63
Code Segment (CS) amp; Instruction Pointer (IP) Registers 67
The Data Segment (DS) Register 69
The Extra Segment (ES) Register 70
Stack Segment (SS) amp; Stack Pointer (SP) Registers 71
Little-Endian Byte-Ordering Rule 74
Definition of Extended Memory 75
=^==_= Contents
Accessing Extended Memory in Real Mode 76
The Bus Unit ; 81
Address Latches and Drivers 81
Instruction Prefetcher and 6-byte Prefetch Queue , 81
Processor Extension Interface 82
Bus Control Logic 83
Data Transceivers 83
80286 Hardware Interface to External Devices 83
The Address Bus
How 80286 Addresses External Locations : 85
The Data Bus 87
The Cardinal Rules 88
Cardinal Rule Number One 88
Cardinal Rule Number Two , 89
Cardinal Rule Number Three 89
The Control Bus 89
Bus Cycle Definition Lines : 90
Bus Mastering Lines 90
Protecting Access To Shared Resource 92
Ready Line 94
Interrupt Lines 95
Processor Extension Interface Lines
The Clock Line : 97
The Reset Line 97
Protected Mode 98
Intro to Protected Mode and Multitasking Operating Systems 99
Segment Register Usage in Protected Mode : 101
Chapter 6: The Reset Logic
The Power Supply Reset 107
Reset Button 108
Shutdown Detect 108
Hot Reset i : 109
Alternate (Fast) Hot Reset Ill
Ctrl-Alt-Del Soft Reset I l l
Chapter 7: The Power-Up Sequence
The Power Supply - Primary Reset Source 113
How RESET Affectsthe Microprocessor 115
Processor Reaction When Output Voltages Stabilize 115
The First Bus Cycle 116
ISA System Architecture
Chapter 8: The 80286 System Kernel: the Engine
The Bus Control Logic :
v; : 119
The Address Latch ::; 124
Address Pipelining : •: :: 123
The Data Bus Transceivers: 124
Data Bus Steering Logic :,; 126
Scenario One - Read Even-Addressed Location in 8-Bit Device 128
Scenario Two - 8-Bit Read from Odd-Addressed Location in 8-Bit Device 129
Scenario Three - 8-Bit Write to Odd-Addressed Location in 8-Bit Device 131
Scenario Four - 16-Bit Write to 8-Bit Device : 132
Scenario Five - 16-Bit Read from 8-Bit Device 133
Scenario Six-8-Bit Read, from 16-Bit Device1 , i34
Scenario Seven - 16-Bit Read from 16-Bit Device 134
Scenario Eight - 8-Bit Write to 16-Bit Device : 134
Scenario Nine - 16-rBit Write to 16-Bit Device 134
The Ready Logic „; 134
Access Time :: 134
Stretching the Transfer Time 135
The Default Ready Timer : 135
Custom Ready Timers 136
Extending trie Default Timing , 137
Shortening the Default Timing -,: 138
Chapter 9: Detailed View of the 80286 Bus Cycle
Address and Data Time Revisited ; 139
The Read Bus Cycle :; ; 141
Bus Cycle A :: 144
Bus Cycle B
The Write Bus Cycle „; 146
The Halt or Shutdown Bus Cycle 150
Halt
Shutdown :, -• 151
Chapter 10: The 80386 DX and SX Microprocessors
Introduction ; ! 153
The 80386 Functional Units 154
General 154
Code Prefetch Unit 155
Instruction Decode Unit 155
Execution Unit : 156
General 156
Contents
_, The Registers 156
General Registers 156
Status, MSW and Instruction Registers 157
Debug Registers : 159
Test Registers 160
Segmentation Unit 160
Paging Unit : 161
Bus Unit : 162
Protected Mode ; ; 162
Page Translation 164
Virtual Paging : 164
Translation Lookaside Buffer 170
Virtual-8086 Mode 172
Automatic Self-Test : 174
80386DX External Interface 175
The Address Bus 175
The Data Bus 183
The Control Bus 184
Bus Cycle Definition Outputs 185
Processor Extension Lines 185
Address Status Output 185
Pipelining Control Input 186
Dynamic Bus Sizing (BS16#) 186
80386SX External Interface 187
Interface Signal Differences 187
A0orBLE# 188
Addressing Scheme, Data Bus Width Ramifications 188
Throughput and Compatibility Considerations 189
Chapter 11: The 80386 System Kernel
Introduction 191
The 80386SX System Kernel 192
The 80386DX System Kernel 194
80386DX System Kernel with Dynamic Bus Sizing 194
Introduction 194
Reading from an 8-Bit Device 196
One-Byte Read from an 8-Bit Device 196
Two-Byte Read from an 8-Bit Device 197
Four-ByteRead from an 8-Bit Device 198
Writing to an 8-Bit Device 200
One-Byte Write to an 8-Bit Device 200
Two-Byte Write to an 8-Bit Device 201
ISA System Architecture
Four-Byte Write to an 8-Bit Device 203
Reading from a 16-Bit Device , : 205
Two-Byte Read from a 16-Bit Device 205
Four-Byte Read from a 16-Bit Device 206
Writing to a 16:Bit Device 207
Two-Byte Write to a 16-Bit Device , 207
Four-Byte Write to a 16-Bit Device 208
Reading from a 32-Bit Device 210
Writing to a 32-Bit Device 211
80386DX System Kernel without Dynamic Bus Sizing 212
Introduction 212
Reading from a 16-Bit Device 214
Two-Byte Read from a 16-Bit Device 214
Four-Byte Read from a 16-Bit Device : 215
Writing to a 16-Bit Device 216
Two-Byte Write to a 16-Bit Device 216
Four-Byte Write to a 16-Bit Device 217
Chapter 12: Detailed View of the 80386 Bus Cycles
The Bus Cycle Types 221
Address Pipelining Overview 222
Memory or I/O Read Bus Cycle 222
Memory or I/O Write Bus Cycle 224
Address Pipelining Example 226
Interrupt Acknowledge Bus Cycle 230
Halt or Shutdown Bus Cycle 230
Part 2: Memory Subsystems
Chapter 13: RAM Memory: Theory of Operation
Dynamic RAM (DRAM) Memory 235
DRAM Addressing Sequence 236
Row and Column Address Source 238
DRAM Addressing Logic 239
Detailed Description of DRAM Addressing Sequence 242
How Data is Stored in DRAM 244
DRAM Refresh 244
Refresh Logic and RAS-only Refresh 245
CAS-before-RAS Refresh 248
Hidden Refresh 248
Self-Refresh 248
Destructive Read: Pre-Charge Delay and Cycle Time 250
• Contents
^ •
DRAM Bank 251
DRAM Bank Width 253
DRAM Error Detection and Correction 256
DRAM Parity 256
Error-Checking-and-Correcting Memory 259
Page-Mode DRAM and Its Variations 259
Page Mode DRAM 259
Enhanced Page Mode DRAM 264
Burst and Nibble Mode DRAM 265
Static Column RAM (SCRAM) 267
Synchronous DRAM 268
Interleaved Memory Architecture 269
Static RAM (SRAM) 271
Chapter 14: Cache Memory Concepts
The Problem 273
The Solution 274
Principles of Locality 277
Temporal Locality 277
Spatial Locality 277
Cache Performance 278
Overall System Performance 278
Cache Consistency 279
Components of a Cache Subsystem 279
Cache Memory 279
Cache Management Logic 281
Cache Memory Directory 281
Intro to Cache Architecture, Coherency, Write Policies and Organization 282
Cache Architectures 283
Look-Through Cache 283
Look-Aside Cache 287
First- and Second-Level Caches 289
Combined (Unified) and Split (Dedicated) Caches 290
Cache Consistency (Coherency) 291
Causes of Cache Consistency Problems 292
Write Policy 292
Write-Through Cache Designs 293
Buffered Write-Through Designs 293
Write-Back Cache Designs 294
Bus Master/Cache Interaction 295
Bus Snooping/Snarfing 295
Coherency via Cache Flushing 297
ISA System Architecture
Software-Enforced Coherency 298
Cache Organization and Size 299
Fully-Associative Cache 299
Direct-Mapped Cache (One-Way Set-Associative) 301
Two-Way Set-Associative Cache 304
Four-Way Set-Associative Cache 307
Least-Recently Used (LRU) Algorithm 307
Cache Line Size 308
Cache Size 310
First-Level Cache Size 310
Second-Level Cache Size 310
Cache Addressing 311
I/O Information Not Cached 311
Non-Cacheable Memory 312
Testing Memory 313
Chapter 15: ROM Memory
ROM Memory — Theory of Operation 315
Introduction 315
Fusible-Link PROM 317
Masked ROM (MROM) 317
Eraseable Programmable Read-Only Memory (EPROM) 318
Electrically Eraseable Programmable Read-Only Memory (EEPROM) 319
Flash EEPROM 320
ROM s Interface to System 320
System Board ROM Memory 322
Testing 322
Shadow RAM 324
Shadow RAM and ROM Occupying Different Address Spaces 324
Shadow RAM and ROM Occupy Same Address Space 325
Double Mapping ROM and Shadow RAM Address Space 325
Recovering Unused ROM Address Space 326
32KB System Board ROM Configuration 327
64KB System Board ROM Configuration 329
ROMs on ISA Cards (Device ROMs) 330
Part 3: The Industry Standard Architecture
Chapter 16: ISA Bus Structure
Introduction 335
Address Bus 338
Data Bus 339
^ • Contents
» •
Bus Cycle Definition 339
Bus Cycle Timing 341
Device Size 343
Reset 344
DMA 345
Interrupts 347
Error Reporting Signal 349
Miscellaneous Signals 350
Chapter 17: Types of ISA Bus Cycles
Introduction 351
Transfers with 8-bit Devices 352
Transfers with 16-bit Devices 355
Standard 16-bit Memory Device ISA Bus Cycle 355
Standard 16-bit I/O Device ISA Bus Cycle 359
O-Wait State Access to 16-bit Memory Device 362
Chapter 18: The Interrupt Subsystem
What Is an Interrupt? 365
Microprocessor Response to Interrupt Request 366
Interrupt Acknowledge Bus Cycles 369
Saving Pointer to Interrupted Program 373
Clearing the Interrupt Enable Flag 378
Jumping to the ISR 378
Resuming the Interrupted Program 379
When One 8259 Interrupt Controller Isn t Enough 383
Servicing Requests to Slave Interrupt Controller 387
Interrupt Table Entry Assignments 388
IRQ2 Redirect , 389
Shareable Interrupts in ISA Machines 391
Generating the Interrupt Request 391
Interrupt Table Initialization - Add-in Devices 392
Shared Interrupt Procedure 393
Phantom Interrupts 394
Programming the 8259 396
Introduction 396
Programming the Registers 396
Non-Maskable Interrupt Requests (NMI) 399
Software Interrupts ? 402
Software Exceptions 402
Software Interrupt Instruction 403
Protected Mode Interrupts 406
ISA System Architecture
Chapter 19: Direct Memory Access (DMA)
DMA Concept 409
DMA Example 410
DMA Controller (DMAC) 414
DMA Transfer Types 414
DMA Transfer Modes 414
Single Transfer Mode 415
Block Transfer Mode 416
Demand Transfer Mode 416
Cascade Mode 417
DMAC Priority Logic 417
DMA Bus Cycle 420
Byte or Word Transfers 423
DMAC Addressing Capability 423
Addressing ISA Memory 427
Addressing Local Bus Memory 428
Address Translation 430
Data Bus Steering 430
DMA Transfer Rate 431
DMAC Initialization During POST 431
Chapter 20: ISA Bus Masters
ISA Bus Master Capability 433
ISA Bus Masters in 80386DX and Higher Systems 435
Address Translation 438
Data Bus Steering 438
Bus Masters and DRAM Refresh 439
Chapter 21: RTC and Configuration RAM
Introduction 441
Accessing the RAM Locations 442
Address Decoder and RTC s Hardware Interface 442
Real-Time Clock Function 443
Using BIOS to Control Real-Time Clock 445
Configuration RAM Usage 446
Chapter 22: Keyboard/Mouse Interface
Keyboard/Mouse Interface 449
Keyboard , 450
Mouse 450
8042 Local I/O Ports 450
Hot Reset 451
^ • Contents
* •
A2QGate 451
Local Port Definition 452
System Interface 453
Command/Status Port 454
Data Port 456
BIOS Routine 457
Chapter 23: Numeric Coprocessor
Introduction 459
Setup , ; 460
With Numeric Coprocessor Installed 460
Numeric Coprocessor Reset 463
Without Numeric Coprocessor Installed (Emulation) 465
Weitek Numeric Coprocessor 467
Introduction 467
Systems Incorporating Just the Weitek
General 467
Weitek Handling of Intel Coprocessor Instructions 467
Systems Incorporating Both Coprocessor Types 468
Chapter 24; ISA Timers
ISA Oscillator, OSC 469
System Timer (Timer 0) 469
Refresh Timer (Timer 1) 471
Speaker Timer (Timer 2) 471
Watchdog Timer : 472
Slowdown Timer , 474
Appendices
I/O Address Map , 479
Glossary of Terms , 491
Index 507
|
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| language | English |
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| spelling | Shanley, Tom Verfasser aut ISA system architecture Tom Shanley and Don Anderson 3. ed. Reading, Mass. u.a. Addison-Wesley 1995 XXV, 515 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier PC system architecture series Architecture - Isa - Micro-Ordinateur - Microprocesseur - Ordinateur - Pc - Systeme Microordinateurs - Bus ram Architektur Anderson, Don Verfasser aut HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006982981&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Shanley, Tom Anderson, Don ISA system architecture Architecture - Isa - Micro-Ordinateur - Microprocesseur - Ordinateur - Pc - Systeme Microordinateurs - Bus ram Architektur |
| title | ISA system architecture |
| title_auth | ISA system architecture |
| title_exact_search | ISA system architecture |
| title_full | ISA system architecture Tom Shanley and Don Anderson |
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| title_full_unstemmed | ISA system architecture Tom Shanley and Don Anderson |
| title_short | ISA system architecture |
| title_sort | isa system architecture |
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