Digital design and synthesis with Verilog HDL:
Gespeichert in:
| Format: | Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
San Jose, CA
Automata Publ. Co.
1993
|
| Ausgabe: | 2. print. |
| Schriftenreihe: | Design automation series
|
| Schlagworte: | |
| Beschreibung: | XII, 375 S. graph. Darst. |
| ISBN: | 096274882X |
Internformat
MARC
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| 300 | |a XII, 375 S. |b graph. Darst. | ||
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| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Logic design |x Data processing | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
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| 700 | 1 | |a Sternheim, Eli |e Sonstige |4 oth | |
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Datensatz im Suchindex
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| building | Verbundindex |
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| callnumber-first | T - Technology |
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| callnumber-sort | TK 47885.7 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| ctrlnum | (OCoLC)31094933 (DE-599)BVBBV010423198 |
| dewey-full | 621.3819532 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3819532 |
| dewey-search | 621.3819532 |
| dewey-sort | 3621.3819532 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 2. print. |
| format | Book |
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| id | DE-604.BV010423198 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T17:52:16Z |
| institution | BVB |
| isbn | 096274882X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006944136 |
| oclc_num | 31094933 |
| open_access_boolean | |
| owner | DE-20 |
| owner_facet | DE-20 |
| physical | XII, 375 S. graph. Darst. |
| publishDate | 1993 |
| publishDateSearch | 1993 |
| publishDateSort | 1993 |
| publisher | Automata Publ. Co. |
| record_format | marc |
| series2 | Design automation series |
| spelling | Digital design and synthesis with Verilog HDL Eli Sternheim ... 2. print. San Jose, CA Automata Publ. Co. 1993 XII, 375 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Design automation series Datenverarbeitung Logic design Data processing Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd rswk-swf VERILOG (DE-588)4268385-3 s DE-604 Sternheim, Eli Sonstige oth |
| spellingShingle | Digital design and synthesis with Verilog HDL Datenverarbeitung Logic design Data processing Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4268385-3 |
| title | Digital design and synthesis with Verilog HDL |
| title_auth | Digital design and synthesis with Verilog HDL |
| title_exact_search | Digital design and synthesis with Verilog HDL |
| title_full | Digital design and synthesis with Verilog HDL Eli Sternheim ... |
| title_fullStr | Digital design and synthesis with Verilog HDL Eli Sternheim ... |
| title_full_unstemmed | Digital design and synthesis with Verilog HDL Eli Sternheim ... |
| title_short | Digital design and synthesis with Verilog HDL |
| title_sort | digital design and synthesis with verilog hdl |
| topic | Datenverarbeitung Logic design Data processing Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Datenverarbeitung Logic design Data processing Verilog (Computer hardware description language) VERILOG |
| work_keys_str_mv | AT sternheimeli digitaldesignandsynthesiswithveriloghdl |