Formal verification of VIPER's ALU:
Abstract: "This research report describes the formal verification of an arithmetic logic unit of the VIPER microprocessor. VIPER is one of the first processors designed using formal methods. A formal model in HOL has been created which models the ALU at two levels: on the higher level, the ALU...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Cambridge
1993
|
| Schriftenreihe: | Computer Laboratory <Cambridge>: Technical report
300 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "This research report describes the formal verification of an arithmetic logic unit of the VIPER microprocessor. VIPER is one of the first processors designed using formal methods. A formal model in HOL has been created which models the ALU at two levels: on the higher level, the ALU is specified as a function taking two 32-bit operands and returning a result; on the lower level, the ALU is implemented by a number of 4-bit slices which should takes [sic] the same operands and returns the same result. The ALU is capable of performing thirteen different operations. A formal proof of functional equivalence of these two levels has been completed successfully The complete HOL text of the ALU formal model and details of the proof procedures are included in this report. It has demonstrated that the HOL system is powerful and efficient enough to perform formal verification of realistic hardware design. |
| Beschreibung: | 78 S. |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV010412421 | ||
| 003 | DE-604 | ||
| 005 | 19960925 | ||
| 007 | t | ||
| 008 | 951009s1993 |||| 00||| engod | ||
| 035 | |a (OCoLC)30408065 | ||
| 035 | |a (DE-599)BVBBV010412421 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 084 | |a DAT 325f |2 stub | ||
| 084 | |a DAT 160f |2 stub | ||
| 100 | 1 | |a Wong, Wai |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Formal verification of VIPER's ALU |
| 264 | 1 | |a Cambridge |c 1993 | |
| 300 | |a 78 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Computer Laboratory <Cambridge>: Technical report |v 300 | |
| 520 | 3 | |a Abstract: "This research report describes the formal verification of an arithmetic logic unit of the VIPER microprocessor. VIPER is one of the first processors designed using formal methods. A formal model in HOL has been created which models the ALU at two levels: on the higher level, the ALU is specified as a function taking two 32-bit operands and returning a result; on the lower level, the ALU is implemented by a number of 4-bit slices which should takes [sic] the same operands and returns the same result. The ALU is capable of performing thirteen different operations. A formal proof of functional equivalence of these two levels has been completed successfully | |
| 520 | 3 | |a The complete HOL text of the ALU formal model and details of the proof procedures are included in this report. It has demonstrated that the HOL system is powerful and efficient enough to perform formal verification of realistic hardware design. | |
| 650 | 7 | |a Computer hardware |2 sigle | |
| 650 | 7 | |a Computer software |2 sigle | |
| 650 | 4 | |a Microprocessors | |
| 830 | 0 | |a Computer Laboratory <Cambridge>: Technical report |v 300 |w (DE-604)BV004055605 |9 300 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-006934255 | ||
Datensatz im Suchindex
| _version_ | 1804124841007120384 |
|---|---|
| any_adam_object | |
| author | Wong, Wai |
| author_facet | Wong, Wai |
| author_role | aut |
| author_sort | Wong, Wai |
| author_variant | w w ww |
| building | Verbundindex |
| bvnumber | BV010412421 |
| classification_tum | DAT 325f DAT 160f |
| ctrlnum | (OCoLC)30408065 (DE-599)BVBBV010412421 |
| discipline | Informatik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01877nam a2200337 cb4500</leader><controlfield tag="001">BV010412421</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">19960925 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">951009s1993 |||| 00||| engod</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)30408065</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV010412421</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 325f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 160f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Wong, Wai</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Formal verification of VIPER's ALU</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Cambridge</subfield><subfield code="c">1993</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">78 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Computer Laboratory <Cambridge>: Technical report</subfield><subfield code="v">300</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Abstract: "This research report describes the formal verification of an arithmetic logic unit of the VIPER microprocessor. VIPER is one of the first processors designed using formal methods. A formal model in HOL has been created which models the ALU at two levels: on the higher level, the ALU is specified as a function taking two 32-bit operands and returning a result; on the lower level, the ALU is implemented by a number of 4-bit slices which should takes [sic] the same operands and returns the same result. The ALU is capable of performing thirteen different operations. A formal proof of functional equivalence of these two levels has been completed successfully</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">The complete HOL text of the ALU formal model and details of the proof procedures are included in this report. It has demonstrated that the HOL system is powerful and efficient enough to perform formal verification of realistic hardware design.</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Computer hardware</subfield><subfield code="2">sigle</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Computer software</subfield><subfield code="2">sigle</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Microprocessors</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Computer Laboratory <Cambridge>: Technical report</subfield><subfield code="v">300</subfield><subfield code="w">(DE-604)BV004055605</subfield><subfield code="9">300</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-006934255</subfield></datafield></record></collection> |
| id | DE-604.BV010412421 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:52:04Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006934255 |
| oclc_num | 30408065 |
| open_access_boolean | |
| physical | 78 S. |
| publishDate | 1993 |
| publishDateSearch | 1993 |
| publishDateSort | 1993 |
| record_format | marc |
| series | Computer Laboratory <Cambridge>: Technical report |
| series2 | Computer Laboratory <Cambridge>: Technical report |
| spelling | Wong, Wai Verfasser aut Formal verification of VIPER's ALU Cambridge 1993 78 S. txt rdacontent n rdamedia nc rdacarrier Computer Laboratory <Cambridge>: Technical report 300 Abstract: "This research report describes the formal verification of an arithmetic logic unit of the VIPER microprocessor. VIPER is one of the first processors designed using formal methods. A formal model in HOL has been created which models the ALU at two levels: on the higher level, the ALU is specified as a function taking two 32-bit operands and returning a result; on the lower level, the ALU is implemented by a number of 4-bit slices which should takes [sic] the same operands and returns the same result. The ALU is capable of performing thirteen different operations. A formal proof of functional equivalence of these two levels has been completed successfully The complete HOL text of the ALU formal model and details of the proof procedures are included in this report. It has demonstrated that the HOL system is powerful and efficient enough to perform formal verification of realistic hardware design. Computer hardware sigle Computer software sigle Microprocessors Computer Laboratory <Cambridge>: Technical report 300 (DE-604)BV004055605 300 |
| spellingShingle | Wong, Wai Formal verification of VIPER's ALU Computer Laboratory <Cambridge>: Technical report Computer hardware sigle Computer software sigle Microprocessors |
| title | Formal verification of VIPER's ALU |
| title_auth | Formal verification of VIPER's ALU |
| title_exact_search | Formal verification of VIPER's ALU |
| title_full | Formal verification of VIPER's ALU |
| title_fullStr | Formal verification of VIPER's ALU |
| title_full_unstemmed | Formal verification of VIPER's ALU |
| title_short | Formal verification of VIPER's ALU |
| title_sort | formal verification of viper s alu |
| topic | Computer hardware sigle Computer software sigle Microprocessors |
| topic_facet | Computer hardware Computer software Microprocessors |
| volume_link | (DE-604)BV004055605 |
| work_keys_str_mv | AT wongwai formalverificationofvipersalu |