A formalisation of the VHDL simulation cycle:
Abstract: "The VHSIC Hardware Description Language (VHDL) has been gaining wide acceptance as a unifying HDL. It is, however, still a language in which the only way of validating a design is by careful simulation. With the aim of better understanding VHDL's particular simulation process an...
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Cambridge
1992
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| Series: | Computer Laboratory <Cambridge>: Technical report
249 |
| Subjects: | |
| Summary: | Abstract: "The VHSIC Hardware Description Language (VHDL) has been gaining wide acceptance as a unifying HDL. It is, however, still a language in which the only way of validating a design is by careful simulation. With the aim of better understanding VHDL's particular simulation process and eventually reasoning about it, we have developed a formalisation of VHDL's simulation cycle for a subset of the language. It has also been possible to embed our semantics in the Cambridge Higher-Order Logic (HOL) system and derive interesting properties about specific VHDL programs." |
| Physical Description: | 24 S. |
Staff View
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| id | DE-604.BV010411561 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:52:03Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006933498 |
| oclc_num | 27028395 |
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| owner_facet | DE-19 DE-BY-UBM |
| physical | 24 S. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| record_format | marc |
| series | Computer Laboratory <Cambridge>: Technical report |
| series2 | Computer Laboratory <Cambridge>: Technical report |
| spelling | Van Tassel, John P. Verfasser aut A formalisation of the VHDL simulation cycle Cambridge 1992 24 S. txt rdacontent n rdamedia nc rdacarrier Computer Laboratory <Cambridge>: Technical report 249 Abstract: "The VHSIC Hardware Description Language (VHDL) has been gaining wide acceptance as a unifying HDL. It is, however, still a language in which the only way of validating a design is by careful simulation. With the aim of better understanding VHDL's particular simulation process and eventually reasoning about it, we have developed a formalisation of VHDL's simulation cycle for a subset of the language. It has also been possible to embed our semantics in the Cambridge Higher-Order Logic (HOL) system and derive interesting properties about specific VHDL programs." Computer hardware sigle Computer software sigle VHDL (Computer hardware description language) Computer Laboratory <Cambridge>: Technical report 249 (DE-604)BV004055605 249 |
| spellingShingle | Van Tassel, John P. A formalisation of the VHDL simulation cycle Computer Laboratory <Cambridge>: Technical report Computer hardware sigle Computer software sigle VHDL (Computer hardware description language) |
| title | A formalisation of the VHDL simulation cycle |
| title_auth | A formalisation of the VHDL simulation cycle |
| title_exact_search | A formalisation of the VHDL simulation cycle |
| title_full | A formalisation of the VHDL simulation cycle |
| title_fullStr | A formalisation of the VHDL simulation cycle |
| title_full_unstemmed | A formalisation of the VHDL simulation cycle |
| title_short | A formalisation of the VHDL simulation cycle |
| title_sort | a formalisation of the vhdl simulation cycle |
| topic | Computer hardware sigle Computer software sigle VHDL (Computer hardware description language) |
| topic_facet | Computer hardware Computer software VHDL (Computer hardware description language) |
| volume_link | (DE-604)BV004055605 |
| work_keys_str_mv | AT vantasseljohnp aformalisationofthevhdlsimulationcycle |