Correct hardware design and verification methods: IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt, Main, Germany, October 2-4, 1995 ; proceedings
Gespeichert in:
| Format: | Tagungsbericht Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Berlin u.a.
Springer
1995
|
| Schriftenreihe: | Lecture notes in computer science
987 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | VIII, 342 S. Ill., graph. Darst. |
| ISBN: | 3540603859 |
Internformat
MARC
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| 245 | 1 | 0 | |a Correct hardware design and verification methods |b IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt, Main, Germany, October 2-4, 1995 ; proceedings |c Paolo E. Camurati ... (eds.) |
| 264 | 1 | |a Berlin u.a. |b Springer |c 1995 | |
| 300 | |a VIII, 342 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Lecture notes in computer science |v 987 | |
| 650 | 4 | |a Circuits intégrés - Vérification - Congrès | |
| 650 | 7 | |a Circuits intégrés à grande échelle - Conception et construction - Informatique - Congrès |2 ram | |
| 650 | 4 | |a Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès | |
| 650 | 7 | |a Conception assistée par ordinateur - Congrès |2 ram | |
| 650 | 7 | |a Hardware |2 gtt | |
| 650 | 7 | |a VHDL |2 inriac | |
| 650 | 7 | |a Vormgeving |2 gtt | |
| 650 | 7 | |a conception matériel |2 inriac | |
| 650 | 7 | |a démonstration théorème |2 inriac | |
| 650 | 7 | |a méthode vérification |2 inriac | |
| 650 | 7 | |a système état fini |2 inriac | |
| 650 | 7 | |a vérification formelle |2 inriac | |
| 650 | 7 | |a vérification matériel |2 inriac | |
| 650 | 4 | |a Integrated circuits -- Very large scale integration -- Computer-aided design -- Congresses | |
| 650 | 4 | |a Integrated circuits -- Verification -- Congresses | |
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| 700 | 1 | |a Camurati, Paolo E. |e Sonstige |4 oth | |
| 710 | 2 | |a International Federation for Information Processing |b Working Group Very Large Scale Integration |e Sonstige |0 (DE-588)307182-0 |4 oth | |
| 711 | 2 | |a CHARME |n 8 |d 1995 |c Frankfurt, Main |j Sonstige |0 (DE-588)2149469-1 |4 oth | |
| 830 | 0 | |a Lecture notes in computer science |v 987 |w (DE-604)BV000000607 |9 987 | |
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| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-006904665 | |
Datensatz im Suchindex
| _version_ | 1820874847444533248 |
|---|---|
| adam_text |
TABLE
OF
CONTENTS
MODEL
CHECKING
WHAT
IF
MODEL
CHECKING
MUST
BE
TRULY
SYMBOLIC
H.
HUNGAR,
OFFIS
OLDENBURG,
GERMANY
O.
GRUMBERG,
THE
TECHNION,
HAIFA,
ISRAEL
W.
DAMM,
OLDENBURG
UNIV.,
GERMANY
.
1
AUTOMATIC
VERIFICATION
OF
THE
SCI
CACHE
COHERENCE
PROTOCOL
U.
STEM,
D.L.
DILL,
STANFORD
UNIV.,
USA
.
21
THEOREM
PROVING
DESCRIBING
AND
VERIFYING
SYNCHRONOUS
CIRCUITS
WITH
THE
BOYER-MOORE
THEOREM
PROVER
L.
PIERRE,
MARSEILLE
UNIV.,
FRANCE
.
35
PROBLEMS
ENCOUNTERED
IN
THE
MACHINE-ASSISTED
PROOF
OF
HARDWARE
P.
CURZON,
CAMBRIDGE
UNIV.,
UK
.
56
FORMALLY
VERIFIED
SYNTHESIS
FORMALLY
EMBEDDING
EXISTING
HIGH
LEVEL
SYNTHESIS
ALGORITHMS
D.
EISENBIEGLER,
R.
KUMAR,
FZI
KARLSRUHE,
GERMANY
.
71
FORMAL
DESIGN
OF
A
CLASS
OF
COMPUTERS
L.G.
WANG,
EDINBURGH
UNIV.,
UK
M.
MENDLER,
UNIV,
OF
DENMARK,
DENMARK
.
84
PROCESS
ALGEBRAS
SYMBOLIC
ANALYSIS
AND
VERIFICATION
OF
CPA
DESCRIPTIONS
M.C.
MCFARLAND,
BOSTON
COLLEGE,
USA
T.J.
KOWALSKI,
AT&T
BELL
LABS.
USA
.
103
A
FOUNDATION
FOR
FORMAL
REUSE
OF
HARDWARE
A.C.
V.
DE
MELO,
H.
BARRINGER,
MANCHESTER
UNIV.,
UK
.
124
FINITE
STATE
SYSTEMS
I
STATE
ENUMERATION
WITH
ABSTRACT
DESCRIPTIONS
OF
STATE
MACHINES
F.
CORELLA,
IBM
RESEARCH,
USA
M.
LANGEVIN,
GMD-SET,
GERMANY
E.
CERNY,
Z.
ZHOU,
X.
SONG,
MONTREAL
UNIV.
146
TRANSFORMING
BOOLEAN
RELATIONS
BY
SYMBOLIC
ENCODING
G.
CABODI,
S.
QUER,
POLIT.
DI
TORINO,
ITALY
P.
CAMURATI,
UDINE
UNIV.,
ITALY
.
161
DESIGN
ERROR
DIAGNOSIS
IN
SEQUENTIAL
CIRCUITS
A.
WAHBA,
D.
BORRIONE,
LAB.
ARTEMIS-IMAG,
GRENOBLE
UNIV.,
FRANCE
.
171
VIII
FINITE
STATE
SYSTEMS
II
TIMING
ANALYSIS
OF
ASYNCHRONOUS
CIRCUITS
USING
TIMED
AUTOMATA
0.
MAIER,
SPECTRE-VERIMAG,
FRANCE
A.
PNUELI,
WEIZMANN
INST.,
ISRAEL
.
189
IMPROVED
PROBABILISTIC
VERIFICATION
BY
HASH
COMPACTION
U.
STEM,
D.L.
DILL,
STANFORD
UNIV.,
USA
.
206
VERIFICATION
ENVIRONMENTS
FORMAL
SUPPORT
FOR
THE
ELLA
HARDWARE
DESCRIPTION
LANGUAGE
H.
BARRINGER,
G.
GOUGH,
MANCHESTER
UNIV.,
UK
B.
MONAHAN,
HARLEQUIN
LTD.,
UK
A.
WILLIAMS,
MANCHESTER
UNIV.,
UK
.
225
VERIFYING
HARDWARE
COMPONENTS
WITHIN
JACK
R.
DE
NICOLA,
ROME
UNIV.,
ITALY
A.
FANTECHI,
S.
GNESI,
S.
LAROSA,
G.
RISTORI,
PISA
UNIV.,
ITALY
.
246
LANGUAGE
CONTAINMENT
LANGUAGE
CONTAINMENT
OF
NON-DETERMINISTIC
W-AUTOMATA
S.
TAGIRAN,
R.
HOJATI,
R.K.
BRAYTON,
UNIV,
OF
CALIFORNIA,
BERKELEY,
USA
.
261
A
PARTIAL-ORDER
APPROACH
TO
THE
VERIFICATION
OF
CONCURRENT
SYSTEMS:
CHECKING
LIVENESS
PROPERTIES
D.
BOLIGNANO,
BULL,
FRANCE
.
278
VHDL
SEMANTICS
OF
A
VERIFICATION-ORIENTED
SUBSET
OF
VHDL
D.
DEHARBE,
D.
BORRIONE,
LAB.
ARTEMIS-IMAG,
GRENOBLE
UNIV.,
FRANCE
.
293
REASONING
ABOUT
VHDL
USING
OPERATIONAL
AND
OBSERVATIONAL
SEMANTICS
K.G.
W.
GOOSSENS,
ROME
UNIV.,
ITALY
.
311
A
SYMBOLIC
RELATION
FOR
A
SUBSET
OF
VHDL
'
87
DESCRIPTIONS
AND
ITS
APPLICATION
TO
SYMBOLIC
MODEL
CHECKING
E.
ENCRENAZ,
LAB.
MASI/IBP,
PARIS,
FRANCE
.
328 |
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| callnumber-raw | TK7874.75.A39 1995 |
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| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 150 |
| classification_tum | DAT 190f |
| ctrlnum | (OCoLC)33103673 (DE-599)BVBBV010370920 |
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| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre_facet | Konferenzschrift 1995 Frankfurt am Main |
| id | DE-604.BV010370920 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T15:06:14Z |
| institution | BVB |
| institution_GND | (DE-588)307182-0 (DE-588)2149469-1 |
| isbn | 3540603859 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006904665 |
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| owner | DE-739 DE-91G DE-BY-TUM DE-384 DE-20 DE-19 DE-BY-UBM DE-634 DE-83 DE-11 DE-188 DE-706 |
| owner_facet | DE-739 DE-91G DE-BY-TUM DE-384 DE-20 DE-19 DE-BY-UBM DE-634 DE-83 DE-11 DE-188 DE-706 |
| physical | VIII, 342 S. Ill., graph. Darst. |
| publishDate | 1995 |
| publishDateSearch | 1995 |
| publishDateSort | 1995 |
| publisher | Springer |
| record_format | marc |
| series | Lecture notes in computer science |
| series2 | Lecture notes in computer science |
| spelling | Correct hardware design and verification methods IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt, Main, Germany, October 2-4, 1995 ; proceedings Paolo E. Camurati ... (eds.) Berlin u.a. Springer 1995 VIII, 342 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 987 Circuits intégrés - Vérification - Congrès Circuits intégrés à grande échelle - Conception et construction - Informatique - Congrès ram Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès Conception assistée par ordinateur - Congrès ram Hardware gtt VHDL inriac Vormgeving gtt conception matériel inriac démonstration théorème inriac méthode vérification inriac système état fini inriac vérification formelle inriac vérification matériel inriac Integrated circuits -- Very large scale integration -- Computer-aided design -- Congresses Integrated circuits -- Verification -- Congresses Hardwareverifikation (DE-588)4214982-4 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1995 Frankfurt am Main gnd-content Hardwareverifikation (DE-588)4214982-4 s DE-604 Camurati, Paolo E. Sonstige oth International Federation for Information Processing Working Group Very Large Scale Integration Sonstige (DE-588)307182-0 oth CHARME 8 1995 Frankfurt, Main Sonstige (DE-588)2149469-1 oth Lecture notes in computer science 987 (DE-604)BV000000607 987 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006904665&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Correct hardware design and verification methods IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt, Main, Germany, October 2-4, 1995 ; proceedings Lecture notes in computer science Circuits intégrés - Vérification - Congrès Circuits intégrés à grande échelle - Conception et construction - Informatique - Congrès ram Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès Conception assistée par ordinateur - Congrès ram Hardware gtt VHDL inriac Vormgeving gtt conception matériel inriac démonstration théorème inriac méthode vérification inriac système état fini inriac vérification formelle inriac vérification matériel inriac Integrated circuits -- Very large scale integration -- Computer-aided design -- Congresses Integrated circuits -- Verification -- Congresses Hardwareverifikation (DE-588)4214982-4 gnd |
| subject_GND | (DE-588)4214982-4 (DE-588)1071861417 |
| title | Correct hardware design and verification methods IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt, Main, Germany, October 2-4, 1995 ; proceedings |
| title_auth | Correct hardware design and verification methods IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt, Main, Germany, October 2-4, 1995 ; proceedings |
| title_exact_search | Correct hardware design and verification methods IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt, Main, Germany, October 2-4, 1995 ; proceedings |
| title_full | Correct hardware design and verification methods IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt, Main, Germany, October 2-4, 1995 ; proceedings Paolo E. Camurati ... (eds.) |
| title_fullStr | Correct hardware design and verification methods IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt, Main, Germany, October 2-4, 1995 ; proceedings Paolo E. Camurati ... (eds.) |
| title_full_unstemmed | Correct hardware design and verification methods IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt, Main, Germany, October 2-4, 1995 ; proceedings Paolo E. Camurati ... (eds.) |
| title_short | Correct hardware design and verification methods |
| title_sort | correct hardware design and verification methods ifip wg 10 5 advanced research working conference charme 95 frankfurt main germany october 2 4 1995 proceedings |
| title_sub | IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt, Main, Germany, October 2-4, 1995 ; proceedings |
| topic | Circuits intégrés - Vérification - Congrès Circuits intégrés à grande échelle - Conception et construction - Informatique - Congrès ram Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès Conception assistée par ordinateur - Congrès ram Hardware gtt VHDL inriac Vormgeving gtt conception matériel inriac démonstration théorème inriac méthode vérification inriac système état fini inriac vérification formelle inriac vérification matériel inriac Integrated circuits -- Very large scale integration -- Computer-aided design -- Congresses Integrated circuits -- Verification -- Congresses Hardwareverifikation (DE-588)4214982-4 gnd |
| topic_facet | Circuits intégrés - Vérification - Congrès Circuits intégrés à grande échelle - Conception et construction - Informatique - Congrès Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès Conception assistée par ordinateur - Congrès Hardware VHDL Vormgeving conception matériel démonstration théorème méthode vérification système état fini vérification formelle vérification matériel Integrated circuits -- Very large scale integration -- Computer-aided design -- Congresses Integrated circuits -- Verification -- Congresses Hardwareverifikation Konferenzschrift 1995 Frankfurt am Main |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006904665&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000000607 |
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