Proceedings of the IEEE 1993 Custom Integrated Circuits Conference: Town and Country Hotel, San Diego, California, May 9 - 12, 1993
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| Sprache: | English |
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Inst. of Electrical and Electroncis Engineers
1993
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| Beschreibung: | Getr. Zählung Ill., graph. Darst. |
| ISBN: | 0780308263 0780308271 078030828X |
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Proceedings of the
IEEE 1993
CUSTOM INTEGRATED CIRCUITS
CONFERENCE
Tschnisos heri senV ‘- irnvi
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BI6LIO THEK
lnventar-Nr :
Sachgebiete:
Standort:
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Town amp; Country Hotel May 9-12, 1993
San Diego, California
Fachbereichsbibliothek Informatik
,TU Darmstadt
59516329
The CICC ’93 is sponsored by the IEEE Electron Devices Society with cooperation from the IEEE Solid
State Circuits Council Its goal is to provide a forum for manufacturers, circuit designers, CAD developers,
and users of ASICs to present and discuss exciting new developments, future trends, and innovative ideas
93CH3214-4
CONTENTS
SESSION 1 SUNDAY EVENING Golden West PAPER#
7:00 NEW DEVICES AND DEVELOPMENTTOOLS Chair: D Perkins Co-Chair: R Saleh
7:05 A Very Low Power Programmable Logic Device—22V10 P Holly and F Zlotnick, Motorola, Inc , Mesa, AZ 1 1
7:25 ASIC Field Programmability Using pFSB® Technology R Slusarczyk and J Lipman, VLSI Technology, Inc , San Jose, CA 1 2
7:45 NEC’s Gate Array Solution for High-Performance Systems C M Smith, NEC Electronics, Inc , Mountain View, CA 1 3
8:05 Automated HDL Generation Within a Datapath Design Framework C-H Chen and C Liu, Compass Design Automation, San Jose, CA 1 4
8:25 ASIC Library Development Tools G Jones, Compass Design Automation, San Jose, CA * 1 5
SESSION 2 SUNDAY EVENING California PAPER #
7:00 NEW PRODUCT APPLICATIONS IN MULTIMEDIA Chair: R Slaymaker Co-Chair: S Wurster
7:05 Development of a Functional System Block (FSB) for Image Compression Applications P Schmidt, VLSI Technology GmbH, Munich Germany 2 1
7:25 A Low-Cost MPEG-Audio Decoder 1C by Texas Instruments G Benbassat, Texas Instruments France, Villeneuve-Loubet, France; and K Cyr and S Li, Texas Instruments, Dallas, TX 2 2
7:45 Genesis Microchip Inc Announces the gm865 x 1, the First of the Acuity Series Image Resizing Products L Greggain, Genesis Microchip, Inc , Markham, Canada 2 3
8:05 Optimised Solutions for Error Corrections in Digital Broadcast Satellites (DBS) A Akibode, VLSI Technology GmbH, Munich, Germany 2 4
8:25 True Top-Down Design via the Comdisco Systems—Synopsys Integrated Tools W Newman and D Varn, Comdisco Systems, Inc , Foster City, CA 2 5
SESSION 3
MONDAY MORNING
Presidio
PAPER#
8:00 WELCOME/OPENING REMARKS
Gregory Ledenbach, General Chairman
Lauren Christopher, Conference Chairman
8:20 CICC 93—TECHNICAL PROGRAM
Resve Saleh, Technical Program Committee Chairman
8:30 KEYNOTE ADDRESS
“Custom 1C Design in Portable Multimedia Applications”
Prof Robert W Broderson, University of California, Berkeley
9:30 PROGRAMMABLE LOGIC DESIGN AUTOMATION AND APPLICATIONS
Chair: R Blake
Co-Chair: K El-Ayat
9:35 A100 MHz FPGA Based Floating Point Adder 3 1
D Narasimhan, D Fernandes and V K Raj, University of Texas, Arlington, TX;and J Dorenbosch, M Bowden
and V Kapoor, Superconducting Supercollider, Dallas, TX
10:00 FPGA Implementation of a Reconfigurable Microprocessor 3 2
J Davidson, University of Quebec, Montreal, Canada
10:25 VHDL Modeling and Simulation of the Back Propagation Algorithm and its Mapping to the RM 3 3
S S Erdogan, A WahabandT H Hong, Nanyang Technological University, Singapore
10:50 CMAP—Technology Mapping for Multiplexor Based FPGA Architectures Using Certificate of 3 4
Generic Boolean Function
S H Lan, Stanford University, Stanford, CA; and R Gopisetty and K R Dharmarajan, Actel Corp , Sunnyvale,CA
11:15 Technology Mapping and Circuit Depth Optiization for Field Programmable Gate Arrays 3 5
S-C Chang and M Marek-Sadowska, University of California, Santa Barbara, CA
11:40 LATE NEWS PAPER
Efficient Boolean Matching in Technology Mapping with Very Large Cell Libraries 3 6
U Schlichtmann, Technical Univ of Munich, Munich, Germany; and F Brglez, MCNC, Research Triangle Park, NC
♦
SESSION 4
MONDAY MORNING
Friars/Padre/Sierra
PAPER#
9:30 MICROPROCESSORS AND NEURAL NETWORKS
Chairman: P Ivey
Co-Chairman: M Nakaya
9:35 VIPER: A25-MHz, 100-MIPS Peak VLIW Microprocessor
J Gray, A Naylor, A Abnous and N Bagherzadeh, University of California, Irvine, CA
4 1
10:00 Self-Checking and Recovering Microprocessor Gl 00FTS for Fault-Tolerant Systems
F Terayama, J Korematsu, F Kitamura, J Hinata and T Enomoto, Mitsubishi Electric Corp , Hyogo, Japan
4 2
10:25 FPA10—A 4 MFlop Floating Point Coprocessor for ARM
P L Harrod, A J Baum, J P Biggs, D W Howard, A J Merritt, H E Oldham, D J Seal and H L Watters, Advanced
RISC Machines, Ltd , Cambridge, UK
4 3
10:50 A Programmable Clock Generator with 50 to 350 MHz Lock Range for Video Signal Processors
J Goto, M Yamashina, T Inoue, B S Shih, Y Koseki, T Horiuchi, N Hamatake, K Kumagai and H Yamada,
NEC Corp , Kanagawa, Japan; and T Enomoto, Chou University, Japan
4 4
11:15
4 5
A Low Power Trainable Analogue Neural Network Classifier Chip
PHW Leong and M A Jabri, University of Sydney, Sydney, Australia
11:40 LATE NEWS PAPER
A VLSI Array Processor for Neural Network Algorithms 4 6
J Beichter, N Bruls, U Ramacher and E Sicheneder, Siemens AG München, Germany; and H Klar,
Technical University of Berlin, Berlin, Germany
SESSION 5 MONDAY MORNING Golden West PAPER#
9:30 ADVANCED DIGITAL SYNTHESIS Chair: J Lipman Co-Chair: S Cravens
9:35 Timing-Driven Resynthesis by Rescheduling and Encoding S C-Y Huang and W Wolf, Princeton University, Princeton, NJ 5 1
10:00 Synthesis of Throughput-Optimized Multichip Architectures C H Gebotys, University of Waterloo, Waterloo, Canada 5 2
10:25 A High Level Synthesis Interface to Erasable Programmable Logic Devices A Doshi and A Goel, Michigan Technological University, Houghton, Ml; and T E Fuhrman, General Motors Corporation, Warren, Ml 5 3
10:50 Generalized ILP Scheduling and Allocation for High-Level DSP Synthesis L E Lucke and K K Parhi, University of Minnesota, Minneapolis, MN 5 4
11:15 Dominance Based Methodologies for Multiple Output CMOS Combinational Gates Synthesis G Buonanno, L Martino, D Sciuto and R Stefanelli, Politecnicodi Milano, Milano, Italy 5 5
11:40 LATE NEWS PAPER A Framework for Fault-Tolerant Microarchitecture Synthesis R Karri and A Orailoglu, University of California, San Diego, CA 5 6
♦
SESSION 6
MONDAY MORNING California PAPER#
9:30 INTEGRATED ANALOG FILTERS Chair: V Gopinathan Co-Chair: D Wayne
9:35 An Analog Circuit Technique for Finding the Median P H Dietz and L R Carley, Carnegie Mellon University, Pittsburgh, PA 6 1
10:00 Low-Voltage Fully-Differential CMOS Swithced-Current Filters R H Zele and D J Allstot, Carnegie Mellon University, Pittsburgh, PA 6 2
10:25 A 5th Order Bilinear Elliptic Switched-Current Filter N C Battersby and C Toumazou, Imperial College of Science, Technology amp; Medicine, London, England 6 3
10:50 TUTORIAL Integrated Continuous-Time Filter Design Y Tsividis, National Technical University of Athens, Athens, Greece 6 4
SESSION 7
MONDAY AFTERNOON
Presidio
PAPER#
2:00 PROGRAMMABLE LOGIC DEVICE ARCHITECTURES
Chair: W Carter
Co-Chair: T Sakurai
2:05 Introducing Redundancy in Field Programmable Gate Arrays 7 1
F Hatori, T Sakurai, K Nogami, K Sawada, M Takahashi, M Ichida, I Yoshii, T Hibi, Y Kawahara, Y Saeki,
H Muroga, A Tanaka and K Kanzaki, Toshiba Corporation, Kawasaki, Japan; and M Uchida, Toshiba
Microelectronics Corporation, Kawasaki, Japan
2:30 Optimized Reconfigurable Cell Array Architecture for High-Performance Field Programmable 7 2
Gate Arrays
B K Britton, W Oswald and S Singh, AT amp;T Bell Labs , Allentown, PA; D D Hill, AT amp;T Bell Labs , Mountain View,
CA; and N-S Woo, AT amp;T Bell Labs , Murray Hill, NJ
2:55 A Dual Granularity and Globally Interconnected Architecture for a Programmable Logic Device 7 3
R Cliff, B Ahanin, L T Cope, F Heile, R Ho, J Huang, C Lytle, S Mashruwala, B Pedersen, R Raman, S Reddy,
V Singhal, C K Sung, K Veenstra and A Gupta, Altera Corporation, San Jose, CA
3:20 Advantages of Heterogeneous Logic Block Architectures for FPGAs 7 4
J He and J Rose, University of Toronto, Toronto, Canada
3:45 A150-mW Dynamic Power 10-ns 22V10 Programmable Logic Device (PLD) 7 5
P Holly, I Sutton, D Tang, W Li, P Butler and F Zlotnick, Motorola, Inc , Mesa, AZ; R Mao, J Vinh, PICO Design,
Sunnyvale, CA; and C Kaplinsky, Serdica, Inc , Palo Alto, CA
4:10 A 10ns, 4000 Gate, 160 Pin CMOS EPLD Developed on a 0 8|xm Process 7 6
R Patel M Wong, D Reese, J Costello and J Turner, Altera Corporation, San Jose, CA
4:35 LATE NEWS PAPER
PREP® Benchmarks for Programmable Logic Devices 7 7
D McCarty, Actel, Sunnyvale, CA; and D Faria and P Alfke, Xilinx, San Jose, CA
--------------♦-------------
SESSION 8
MONDAY AFTERNOON_______________________Friars/Padre/Sierra___________________________PAPER#
2:00 MACROMODELING AND SIMULATION
Chair: K Mayaram
Co-Chair: D Dumlugol
2:05 Macromodeling BiCMOS Gates for Circuit Optimization 8 1
D-P Chen and M Banu, AT amp;T Bell Labs , Murray Hill, NJ; and C Zukowski, Columbia University, New York, NY
2:30 An Efficient Macromodel for Static CMOS Multi-Port Memories 8 2
P Landsberg, C Tretz and C Zukowski, Columbia University, New York, NY
2:55 An FFT-Based Approach to Including Non-Ideal Ground Planes in a Fast 3-D Inductance 8 3
Extraction Program
J R Phillips, M Kamon and J White, MIT, Cambridge, MA
3:20 Mixed-Mode Simulation of Phase-Locked Loops 8 4
BAA Antao, Vanderbilt Univ , Nashville, TN; F M El-Turky and R H Leonwich, AT amp;T Bell Labs , Allentown, PA
3:45 Mixed-Level Circuit and Device Simulation on a Distributed-Memory Multicomputer 8 5
D A Gates, P K Ko and D O Pedersen, University of California, Berkeley, CA
4:10 Design and Implementation of a Prototype Hybrid Simulation Environment 8 6
P K Mozumder, Texas Instruments, Inc , Dallas, TX
4:35 Acceptance Sampling: An Efficient, Accurate Method for Estimating and Optimizing Parametric 8 7
Yield
N J Elias, Philips Laboratories, Briarcliff Manor, NY
SESSION 9
MONDAY AFTERNOON
Golden West
PAPER #
2:00 PERFORMANCE DRIVEN PHYSICAL DESIGN AUTOMATION
Chair: S Mori
Co-Chair: G Buurma
2:05 PAS: A Stand Alone Placement Annotation System for High Speed Designs 9 1
X-M Xiong, Cadence Design Systems, Inc , San Diego, CA; J Hardin, AMCC, San Diego, CA; and C-K Cheng,
University of California, La Jolla, CA
2:30 Modifying the Netlist after Placement for Performance Improvement 9 2
A Ginetti and D Brasen, Compass Design Automation, Sophia Antipolis, France
2:55 Performance-Driven Layout through Device Sizing 9 3
Y You, B Roetcisoender, A Cheng, R McGehee and S Sugiyama, Cascade Design Automation, Bellevue, WA
3:20 Delay amp; Area Optimization for Discrete Gate Sizes under Double-Sided Timing Constraints 9 4
W Chuang and I N Hajj, University of Illinois, Urbana, IL;andS S Sapatnekar, Iowa State University, Ames, IA
3:45 A High Density Datapath Layout Generation Method under Path Delay Constraints 9 5
H Nakao, O Kitada, M Hayashikoshi, K Okazaki and Y Tsujihashi, Mitsubishi Electric Corp , Itami, Japan
4:10 Skew Reduction in Clock Trees Using Wire Width Optimization 9 6
N Menezes, A Balivada, S Pullelaand L T Pillage, University of Texas, Austin, TX
4:35 A Combined Eigenvector Tabu Search Approach for Circuit Partitioning 9 7
S Areibi and A Vannelli, University of Waterloo, Waterloo, Canada
----------------♦-------------
SESSION 10
MONDAY AFTERNOON____________________________California_________________________________PAPER #
2:00 HARD DISK DRIVE ELECTRONICS
Chair: A Barlow
Co-Chair: J Tandon
2:05 A 24 Mbit/s 1 7 Read Channel Combo for Disk-Drive Applications 10 1
K Lam, L Buchholz, J-G Chern, R Contreras, G DeVierman, S Dendinger, G Gorman, R Masumoto, P Okada,
T Shimanuki and S Ueda, Silicon Systems, Inc , Tustin, CA
2:30 A 3-5 5V CMOS 32 Mb/s Fully-Integrated Read Channel for Disk-Drives 10 2
C Petersen, P Cheung, T-S Chung, K-H Loh, W Guo, L Pycior, M Robinson, Inti Microelectronic Products,
Pleasanton, CA; K Tomioka, K Miyashita, Asahi Kasei Microsystems Co , Ltd , Kanagawa, Japan
2:55 CMOS Implementation of a Viterbi Detector for Hard Disk Drives 10 3
P A Ziperovich, Quantum Corp , Milpitas, CA; and J K Wolf, University of California, La Jolla, CA
3:20 A 7MB/Sec (65 MHz), Mixed-Signal, Magnetic Recording Channel DSP Using Partial Response 10 4
Signaling with Maximum Likelihood Detection
R Philpott, R Kertis, R Richetta, T Schmerbeckand D Schulte, IBM Corporation, Rochester, MN
3:45 A High Performance Digital Read Channel for Hard Disk Drives Using PRML Techniques 10 5
S Moore, GEC Plessey Semiconductors, Scotts Valley, CA
4:10 An Integrating Servo Demodulator For Hard Disk Drives 10 6
R Shariatdoust, K Nagaraj, J Khoury and S Daubert, AT amp;T Bell Labs , Allentown, PA; and D Fasen,
Hewlett Packard Co
SESSION 11
TUESDAY MORNING
Presidio
PAPER#
8:30 VLSI FOR VIDEO MULTIMEDIA
Chair: N Weste
Co-Chair: L Christopher
8:35 TUTORIAL
Video Compression and VLSI 11 1
B Ackland, AT amp;T Bell Labs , Holmdel, NJ
9:25 A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video 11 2
S Uramoto, A Takabatake, M Suzuki, H Sakurai and M Yoshimoto, Mitsubishi Electric Corporation, Itami, Japan
9:50 A Motion Video Compression LSI with Distributed Arithmetic Architecutre 11 3
Y Tokuno, H Mizutani, M Yamazaki and H Masaki, OKI Electric Industry Co , Ltd , Tokyo, Japan
10:15 A Single Chip Multistandard Video Codec 11 4
S Bose, S Purcell andT Chiang, C-Cube Microsystem, Milpitas, CA
10:40 INVITED
CMOS Image Sensors for Multimedia Applications 11 5
P B Denyer, D Renshaw, G Wang and M Lu, University of Edinburgh, Edinburgh, UK
♦
SESSION 12
TUESDAY MORNING_______________________________Friars/Padre/Sierra___________________________________PAPER#
8:30 HIGH PERFORMANCE CIRCUITS AND GRAPHICS PROCESSORS
Chair: A Kurosawa
Co-Chair: M Mittal
8:35 3 3V Novel Circuit Techniques for a 2 8-Million-Transistor BiCMOS RISC Processor 12 1
F Murabayashi, T Yamauchi, M Iwamura, T Hotta, Y Kobayashi, T Nakano, K Mori, T Shimizu, R Satomura,
S Mitani, K Shiozawa, A Yamagiwa andT Hayashi, Hitachi Ltd , Ibaraki, Japan; and N Kitamura, Hitachi VLSI
Eng , Corp
9:00 A 64-bit Adder by Pass Transistor BiCMOS Circuit 12 2
K Ueda, H Suzuki, K Suda, Y Tsujihashi and H Shinohara, Mitsubishi Electric Corporation, Itami, Japan
9:25 A CMOS Signal Multiplier Using Wave Pipelining 12 3
V Nguyen, W Liu, C T Gray and R Cavin, North Carolina State University, Raleigh, NC
9:50 A 2 4-ns, 16-bit, 0 5-^m CMOS Arithmetic Logic Unit for Microprogrammable Video Signal 12 4
Processor LSIs
K Suzuki, M Yamashina, J Goto, T Inoue, Y Koseki, T Horiuchi, N Hamatake, K Kumagai and H Yamada,
NEC Corporation, Kanagawa, Japan; T Enomoto, Chuo University, Japan
10:15 An Outline Font Rendering Processor with an Embedded RISC CPU for High-Speed Hint 12 5
Processing
T Kawata, K Kawauchi, N Miyakawa, I Kawazome, H Yasumatsu, S Hagaand M Takenaka, Fuji Xerox Co , Ltd,
Kanagawa, Japan
10:40 A 300-MHz, 16-bit, 0 5-|xm BiCMOS Digital Signal Processor Core LSI 12 6
M Nomura, M Yamashinam, J Goto, T Inoue, K Suzuki, M Motomura, Y Koseki, B S Shih, T Horiuchi,
N Hamatake, K Kumagai and H Yamada, NEC Corporation, Kanagawa, Japan; and T Enomoto,
Chuo University, Japan
11:05 Hexagonal Sensor with Imbedded Analog Image Processing for Pattern Recognition
M Tremblay, M D’Anjou andD Poussart, Univ Laval, Quebec, Canada
12 7
SESSION 13
TUESDAY MORNING
Golden West
PAPER#
8:30 DESIGN AUTOMATION FOR ANALOG AND MIXED SIGNAL ICs Chair: P Ainslie Co-Chair: H-F S Law
8:35 TUTORIAL
Analog Design Automation: Where Are We? Where Are We Going? R A Rutenbar, Carnegie Mellon Univ , Pittsburgh, PA 13 1
9:25 A Multi-Representational Design Data Capture System K Yamagishi and M Sekine, Toshiba Corp , Kawasaki, Japan 13 2
9:50 A Spreadsheet Interface for Analog Design Knowledge Capture and Re-Use R K Henderson, L Astier, A ElKhalifa and M Degrauwe, CSEM, Neuchatel, Switzerland 13 3
10:15 A System for Analog Circuit Design that Stores and Re-uses Design Procedures T Morie, H Onodera and K Tamaru, Kyoto Univ , Kyoto, Japan 13-4
10:40 Flow-Driven Graphical User Interface for Parametric and Statistical Design Optimization C Guardiani and J Benkoski, SGS-Thomson Microelectronics, Milano, Italy 13 5
11:05 SYSCHECK: A User-Programmable Mixed-Mode Verification Tool M Hinners, C Meixenberger, L Astier and M Degrauwe, CSEM, Neuchatel, Switzerland 13 6
♦
SESSION 14
TUESDAY MORNING______________________________California__________________________________PAPER#
8:30 ANALOG MODELING AND SIMULATION
Chair: C Zukowski
Co-Chair: M Hotta
8:35 INVITED
MOSFET Modeling for Analog Circuit CAD: Problems and Prospects 14 1
Y Tsividis, Natl Technical Univ of Athens, Athens, Greece; and K Suyama, Columbia Univ , New York, NY
9:00 A Robust Physical and Predictive Model for Deep-Submicrometer MOS Circuit Simulation 14 2
J H Huang, Z H Liu, P K KoandC Hu, Univ of California, Berkeley, CA; and M C Jeng, Cadence Design
Systems, Santa Clara, CA
9:25 Advanced VLSI Circuit Simulation using the BSIM plus Model 14 3
S M Gowda, B J Sheu and C-H Chang, Univ of Southern California, Los Angeles, CA
9:50 Characterization, Modeling and Minimization of Transient Threshold Voltage Shifts in MOSFETs 14 4
T L Tewksbury, Analog Devices Semiconductor, Wilmington, MA; and H-S Lee, MlT Cambridge, MA
10:15 Performance Optimization of Analog Integrated Circuits by Device Sizing and its Application 14 5
to PseudoSynthesis
N S Nagaraj, Texas Instruments, Bangalore, India
10:40 ACAD: A Hierarchical Approach to CMOS Design Analysis 14 6
B A Richman, American Microsystems, Inc , Pocatello, ID; and P J Windley, Univ of Idaho,, Moscow, ID
11:05 LATE NEWS PAPER
Low-Frequency Symbolic Analysis of Large Analog Integrated Circuits 14
J-J Hsui, C Sechen, Univ of Washington, Seattle, WA
11:20 LATE NEWS PAPER
A New and Efficient Transient Noise Analysis Technique for Simulation of CCD Image Sensors 14
or Particle Detectors
P Bolcato and M S Tawfik, Anacad, Meylan, France; R Poujois, LETI (CEA), Grenoble, France;and P Jarron,
CERN, Geneva, Switzerland
♦
SESSION 15
TUESDAY AFTERNOON
Presidio
PAPER#
2:00 DIGITAL FILTER AND SPECIAL PURPOSE DSP CIRCUITS
Chair: R Jain
Co-Chair: N Weste
2:05 TUTORIAL
Cost, Power, and Parallelism in Speech Signal Processing 15 1
R F Lyon, Apple Computer, Cupertino, CA
2:55 Digital Filter Design for Compact On-Chip Oversampling A/D Conversion 15 2
M F Mar and R W Broderson, Univ of California, Berkeley, CA
3:20 A Reconfigurable Video Ghost Cancelling Filter Chip 15 3
W Lin and E Campbell, David Sarnoff Research Center, Princeton, NJ; P Knutson, Thomson Consumer
Electronics, Indianapolis, IN; and C D Richardson, D Smalley and F Vogler, Texas Instruments, Norcross, GA
3:45 HDTV Data Carrier Separation Using a Multiplexing Filter 15 4
M Caldwell, S Parikh and R Angle, David Sarnoff Research Center, Princeton, NJ; and K Kindsfater, Univ
of California, Los Angeles, CA
4:10 VINCI: VLSI Implementation of the New Secret-Key Block Cipher Idea 15 5
A Curiger, H Bonnenberg, R Zimmerman, N Felber, H Kaeslin and W Fichtner, Swiss Federal Inst, of
Technology, Zurich, Switzerland
4:35 Programmable Facsimile Image Processor Including Fuzzy-Based Decision 15 6
B W Lee, J W Lee, S H Bae, S K Kim and I H Hwang, Samsung Electronics, Co , KyungGi-Do, Korea; and
J H Kim, Pusan Univ , Pusan, Korea
♦
SESSION 16
TUESDAY AFTERNOON______________________Friars/Padre/Sierra____________________________PAPER #
2:00 ADVANCED COMMUNICATION LSIs
Chair: D Embree
Co-Chair: S Wurster
2:05 1 8V CMOS Analog Compandor with 80 dB Dynamic Range 16 1
S Shioda, M Sahoda, M Aketo, K Ohsawa, Y Fujita and T lida, Toshiba Semiconductor Sys Eng , Kawasaki,
Japan; H Kishigami, H Shin and M Ishida, Toshiba Micro-Electronics Center, Kawasaki, Japan; and H Tanimoto,
Toshiba R amp;D Ctr , Kawasaki, Japan
2:30 A Low-Power TDMA PCS Wireless Modem Chip in 0 6-Micron 3-V CMOS 16 2
R R Cordell, A F Kwan, K Ramachandran, N R Sollenberger, P M Benjamin and D Rappaport, Bell
Communications Research, Red Bank, NJ
2:55 A 200 MHz CMOS Digital Radio Frequency Memory Chip with Analog Output 16 3
P Ingelhag and R Sundblad, SiCon AB, Linköping, Sweden; and I Soderquist, SAAB Missiles AB, Linköping,
Sweden
3:20 A Direct-Sequence Spread Spectrum Transceiver Chip 16 4
D Avidor, S-S Hang and J Omura, Cylink Corp , Sunnyvale, CA
3:45 A Programmable VLSI Neural Network Processor for Digital Communications 16 5
J Choi, S H Bang and B J Sheu, Univ of Southern California, Los Angeles, CA
4:10 A 60-Mbaud Adaptive Transversal Equalizer in 1 0-|xm CMOS for QAM Digital Modems 16 6
F Lu and H Samueli, Univ of California, Los Angeles, CA
4:35 A 300 MHz BiCMOS Serial Data Transceiver 16-7
B Thompson and H-S Lee, MIT, Cambridge, MA; and L DeVito, Analog Devices, Wilmington, MA
SESSION 17 TUESDAY AFTERNOON Golden West PAPER#
2:00 AUTOMATIC LAYOUT GENERATION AND ANALYSIS Chair: T Yanagawa Co-Chair: R Maxwell
2:05 Optimum Stacked Layout for Analog CMOS ICs E Malavasi and D Pandini, DEI-Univ di Padova, Padova, Italy; and V Liberali, Univ di Pavia, Pavia, Italy 17 1
2:30 An Improved Algorithm of Transistors Pairing for Compact Layout of Non-Series-Parallel CMOS Networks H Zhang and K Asada, Univ of Tokyo, Tokyo, Japan 17 2
2:55 Performance-Driven Compaction for Analog Integrated Circuits E Felt, E Charbon and A Sangiovanni-Vincentelli, Univ of California, Berkeley, CA; and E Malavasi, Univ di Padova, Padova, Italy 17 3
3:20 Power Distribution Synthesis for Analog and Mixed-signal ASICs in RAIL B R Stanisic, R A Rutenbar and L R Carley, Carnegie Mellon Univ , Pittsburgh, PA 17 4
3:45 Resistance Extraction along the Current Flow L Ladageand R Leupers, Univ Dortmund, Dortmund, Germany 17 5
4:10 HCNC: High Capacity Netlist Compare R Razdan, Harvard Univ /Digital Equipment Corp , Princeton, MA 4 17 6
SESSION 18 TUESDAY AFTERNOON California PAPER#
2:00 AWE AND SIMULATION ALGORITHMS Chair: D Dumlugol Co-Chair: B Sheu
2:05 TUTORIAL
AWE Inspired V Raghavan and R A Rohrer, Carnegie Mellon Univ , Pittsburgh, PA; M M Alaybeyi, J E Bracken and J Y Lee, Performance Signal Integrity, Pittsburgh, PA; and L T Pillage, University of Texas, Austin, TX 18 1
2:55 Finite-Pole Macromodels of Transmission Lines for Circuit Simulation S-Y Kim, N Gopal and L T Pillage, Univ of Texas, Austin, TX 18 2
3:20 Rapid Simulation of Substrate Coupling Effects in Mixed-Mode ICs N K Verghese and D J Allstot, Carnegie Mellon Univ , Pittsburgh, PA; and S Masui, Nippon Steel Corp , Sagamihara, Japan 18 3
3:45 AWEswit: A Switched Capacitor Circuit Simulator R J Trihy and R A Rohrer, Carnegie Mellon Univ , Pittsburgh, PA 18 4
4:10 Frequency-Domain Analysis of Switched Capacitor Circuits Containing Nonidealities J Singh and R Saleh, Univ of Illinois, Urbana, IL 18 5
SESSION 19
TUESDAY EVENING
Presidio
8:00 EVENING PANEL
Personal Communications In The Next Decade:
Which Technologies Will You Be Carrying in Your Pocket?
Moderator: H Samueli, UCLA
SESSION 20
TUESDAY EVENING Friars/Padre/Sierra
8:00 EVENING PANEL
I C Design in the Nineties: Professional Challenge or Assembly Line Burnout?
Moderator: L Starr, Ford Microelectronics, Inc
♦
SESSION 21
TUESDAY EVENING Golden West
8:00 EVENING PANEL
First Time Shippable Silicon—Fact or Fiction?
Moderator: N Weste, TLW, Inc
♦
SESSION 22
TUESDAY EVENING California
8:00 EVENING PANEL
The Analog and Mixed-Signal Bottleneck in the 90’s How to Resolve It?
Moderator: D Dumlugol, Cadence Design Systems
SESSION 23
WEDNESDAY MORNING
Presidio
PAPER#
8:30 ADVANCES IN GATE ARRAYS
Chair: B Fitzgerald
Co-Chair: G Sporzynski
8:35 A One Million-Circuit CMOS ASIC Logic Family 23 1
R Gregor, C Ng, J Libous, E Carter, R Beaudoin, A Chu, D Grindel, J Kinney, M Lee, L Mentos, J Oppold,
M Russell, A Secor and G Yenik, IBM Corp , Endicott, NY
9:00 0 5 ixmlM Gate CMOS SOG 23 2
N Ikeda, A Ishibashi, H Maeno, S Matsue, K Asahina, T ArakawaandS Kato, Mitsubishi Electric Corp ,
Itami, Japan
9:25 A 30-ps Jitter, 3 6-}is Locking, 3-Volt Digital PLL for CMOS Gate Arrays 23 3
U Ko, S A Wichman and S Castrianni, Texas Instruments, Inc , Dallas, TX
9:50 High-Performance ECL Gate Arrays with Compiled and Embedded SRAM Using an Ocean-of- 23 4
Cells Architecture
D Gray, D Beeson, G Davis, D Hutchings, P Thai and T S Wong, Synergy Semiconductor, Santa Clara, CA;
T Kuroda, M Nakamura and M Noda, Toshiba Corp , Kawasaki, Japan
10:15 Interface Techniques for Embedding Custom Mega Cells in a Gate Array 23 5
L Ashby, Motorola, Inc , Chandler, AZ
10:40 A Planar Type EEPROM Cell Structure by Standard CMOS Process for Integration with Gate 23 6
Array, Standard Cell, Microprocessor and for Neural Chips
K Ohsaki, N Asamoto and S Takagaki, IBM Japan, Yasu, Japan
11:05 A Fully-Complementary BiCMOS Array for Mixed Analog/Digital Applications
M Declercq, P Duchene, H Ballane, M Grigorie, T Reimann andT Baechler, Swiss Fed Inst, of Technology,
Lausanne, Switzerland
♦
SESSION 24
WEDNESDAY MORNING__________________________Friars/Padre/Sierra_______________________________PAPER#
8:30 1C FABRICATION TECHNOLOGY
Chair: M Beunder
Co-Chair: I Kizilyalli
8:35 INVITED
High Performance BiCMOS Technology 24 1
T M Liu and R G Swartz, AT amp;T Bell Labs , Holmdel, NJ; T-Y Chiu, AT amp;T Bell Labs , Murray Hill, NJ
9:00 INVITED
A BiCMOS 0 8 p,m Process with a Toolkit for Mixed-Mode Design 24 2
D Stolfa, R Reuss, J Ford, B Cosentino, D Monk, F Shapiro, D Lamey and C Dragon, Motorola, Inc , Mesa, AZ
9:25 A08 Micron BiCMOS Technology for ASIC Applications 24 3
T E Ham, J W Osenbach, M J Thoma, S C Vitkavage, J J Nagy, B L Morris, D C Dennis, P F Bechtold,
D M Boulin and J W Kearney, AT amp;T Bell Labs , Allentown, PA
9:50 0 3 |xm Mixed Analog/Digital CMOS Technology for Low-Voltage Operation 24 4
M Miyamoto, T Ishii, R Nagai, T Nishida and K Seki, Hitachi, Ltd , Tokyo, Japan
10:15 A Modular Merged Technology Process Including Submicron CMOS Logic: Nonvolatile 24 5
Memories, Linear Functions, and Power Components
M C Smayling, J Reynolds, D J Redwine and S Keller, Texas Instruments, Inc , Houston, TX; G Falessi,
Texas Instruments France, Villeneuve Loubet, France
10:40 Design and Optimization of High-Voltage CMOS Devices Compatible with a Standard 5V
CMOS Technology
M Declercq, F Clement, M Schubert, A Harb and M Dutoit, Swiss Federal Institute of Technology, Lausanne,
Switzerland
11:05 LATE NEWS PAPER
Integration of High Voltage Transistors into a15 Micron CMOS Process for LCD Driver
Applications
F Myers, J Sutor, P Tam and H-Y Tsoi, Motorola, Inc , Mesa, AZ; and R Trahan, Motorola, Inc , Austin, TX
-----------------------------------
24 6
24 7
SESSION 25
WEDNESDAY MORNING_______________________Golden West_____________________________PAPER#
8:30 MEMORY AND SPECIAL LOGIC CHIPS
Chair: I Scott
Co-Chair: B Fitzgerald
8:35 A 64kB BiCMOS Cache Controller amp; Memory (CCM) 25 1
T Kobayashi, H Nojima, M Konno, M Igarashi, S Kamano, K Kobayashi, K Shimoda, T Shidei, M Kumazawa,
T Mori and S Kurotsu, OKI Electric Industry Co , Ltd , Tokyo, Japan
9:00 A High Performance / Low Power 16K-Byte 4-Way Set Associative Integrated Cache Macro 25 2
K Y Nguyen, IBM Corp , East Fishkill, NY; and R Flaker, A Roberts, T Holman, R Benson, D Lavalette,
M Robillard, D Nietupski and A Davis, IBM Corp , Burlington, VT
9:25 An Adjustable Output Driver With Self-Recovered Vpp Generator for 4M x 16 DRAM 25 3
K Furutani, H Miyamoto, Y Morooka, M Suwaand H Ozaki, Mitsubishi Electric Corp , Itami, Japan
9:50 1 5V High Speed Read Operation and Low Power Consumption Circuit Technology for EPROM 25 4
and Flash-EEPROM
O Matsumoto, K Miki, T Mizutani and M Tamaoki, Toshiba Semiconductor Sys Eng Ctr , Kawasaki, Japan;
A Wada and M Sato, Toshiba Micro-electronics Corp , Kawasaki, Japan
10:15 A 3 3V ASIC for Mixed Voltage Application with Shut Down Mode 25 5
M Ueda, H Oshikawa, M Yamamoto, Y Tokuda, T Saitoh and M Nishihara, IBM Japan, Ltd , Shiga-ken, Japan;
A Carl, J ladanza, M Nelson K Key, R Kilmoyerand F Jaquish, IBM Corp , Essex Junction, VT
10:40 A 200 MHz 8Kb SRAM Macro for Video Applications 25 6
T Williams, L Bilodeau, R Burroughs, R Fürst, B Pokorny and G Schroer, IBM Corp , Essec Junction, VT
11:05 A Programmable Power Metering Chip 25 7
Y-M Lin and E L Davies, Silicon Systems, Inc , Nevada City, CA; RWM Blasco, R amp;L Associates, Auburn, CA;
D Chan, Consultant, Folsom, CA; and M L Munday and R C Hemminger, ABB PowerT amp;D Co , Inc , Raleigh, NC
11:30 LATE NEWS PAPER
CMOS Fuzzy Logic Controller in Current Mode 25 8
L Lemaitre, M J Patyra and D Mlynek, Swiss Federal Inst, of Technology, Lausanne, Switzerland
♦
SESSION 26
WEDNESDAY MORNING California PAPER#
8:30 TEST
Chair: S Quigley
Co-Chair: P Fang
8:35 Test of a 622 MHz Hybrid Module for ATM Network Using a 200 MHz Validation Station
J Bulone, A Chion and M Diaz Nava, SGS-Thomson, Grenoble, France
26 1
26 2
9:00 A New Design for Testability Method: Clock Line Control Design
S-H Baeg and W A Rogers, Univ of Texas, Austin, TX
9:25 FUNTASSI: A Functional Test Generation Assistant 26 3
K Kohno and M Sekine, Toshiba Corp , Kawasaki, Japan
9:50 IDDQ Test Results on a Digital CMOS ASIC 26 4
G Schiessler and C Spivak, AT amp;T Bell Labs , Allentown, PA; and S Davidson, AT amp;T Bell Labs , Princeton, NJ
10:15 A New BIST Scheme for CMOS PLAs 26 5
V Chandramouli and R K Gulati, Ford Microelectronics, Inc , Colorado Springs, CO; and R Dandapani, Univ
of Colorado, Colorado Springs, CO
10:40 Special Applications of the Voting Model for Bridging Faults 26 6
S D Millman, Motorola, Tempe, AZ; and J M Acken, Intel Corp , Santa Clara, CA
11:05 LATE NEWS PAPER
Computation of Exact Random Pattern Detection Probability 26 7
H Farhat, Univ of Nebraska, Omaha, NE; and A Lioy and M Poncino, Politecnicodi Torino, Torino, Italy
--------------♦------------
SESSION 27
WEDNESDAY AFTERNOON______________________Presidio________________________________PAPER#
1:30 HIGH PRECISION TIMING CIRCUITS
Chair: K Au
Co-Chair: L Starr
1:35 Multi-Frequency Zero-Jitter Delay-Locked Loop 27 1
A Efendovich, Y Afek, C Sella and Z Bikowski, National Semiconductor (I C ) Ltd , Herzlia, Israel
2:00 Cell Based Fully Integrated CMOS Frequency Synthesizers 27 2
M J Bayer, T F Chomicz, N K Garg, F James, P W McEntarfer, D Mijuskovic and J A Porter, Motorola, Inc ,
Chandler, AZ
2:25 A High Precision (+ / - 100 ppm) CMOS Clock Generator for Optimum Sampling of Analog RGB 27 3
Data
A Terukina, Y Suzuki, T Nozawa, S Koyama, A Hino and A Moritani, IBM Japan, Ltd , Kanagawa, Japan
2:50 A BICMOS 50-MHz Voltage-Controlled Oscillator with Quadrature Outputs 27 4
F L Martin, Motorola, Inc , Plantation, FL
3:15 CMOS Sampler with 1 Gbit/s Bandwidth and 25 ps Resolution 27 5
W Van Noije, C T Gray, W Liu, R K Cavin and W J Farlow, North Carolina State University, Raleigh, NC; and
T A Hughes, IBM Corporation, Research Triangle Park, NC
3:40 1 16 GHz Dual-Modulus 1 2 |xm CMOS Prescaler 27 6
R Rogenmoser, N Felber, W Fichtner and Q Huang, Swiss Federal Institute of Technology, Zurich, Switzerland
4:05 Metastability Behavior of Mismatched CMOS Flip-Flops Using State Diagram Analysis 27 7
WAM Van Noije, W T Liu and J Navarro, Jr , North Carolina State University, Raleigh, NC
SESSION 28
WEDNESDAY AFTERNOON Friars/Padre/Sierra PAPER #
1:30 DATA CONVERTERS
Chair: D Allstot
Co-Chair: V Gopinathan
A100 MHz 8 Bit CMOS Interpolating A/D Converter
M Steyaert, R Roovers and J Craninckx, K U Leuven, Heverlee, Belgium
1:35
28 1
28 2
2:00 An Enhanced Successive-Approximation Circuit for A/D Conversion
C M Webster and D T Comer, Penn State Harrisburg, Middletown, PA
2:25 A CMOS Triple 9-Bit 180 MHz DAC for HDTV Applications 28 3
D Draxelmayr, Entwicklungszentrum fur Mikroelektronik, Villach, Austria
2:50 A Single-Chip Stereo Audio CODEC 28 4
K Hamashita, Asahi Kasei Microsystems Co , Ltd , Atsugi, Japan; and E Swanson, Crystal Semiconductor Corp ,
Austin, TX
3:15 A High Resolution Sigma-Delta Modulator with Extended Dynamic Range 28 5
L A Williams, III and B A Wooley, Stanford University, Stanford, CA
3:40 A BiCMOS Time Interval Digitizer for High-Energy Physics Instrumentation 28 6
M J Loinaz and B A Wooley, Stanford University, Stanford, CA
------------------*----------------
SESSION 29
WEDNESDAY AFTERNOON______________________________Golden West______________________________________PAPER#
1:30 OPTICAL AND ELECTRICAL INTERCONNECT AND INTERFACE CIRCUITS
Chair: C-K Cheng
Co-Chair: W Ste
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| spelling | Custom Integrated Circuits Conference 15 1993 San Diego, Calif. Verfasser (DE-588)5102938-8 aut Proceedings of the IEEE 1993 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 9 - 12, 1993 New York, NY Inst. of Electrical and Electroncis Engineers 1993 Getr. Zählung Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Integrated circuits Congresses (DE-588)1071861417 Konferenzschrift gnd-content HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006899476&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings of the IEEE 1993 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 9 - 12, 1993 Integrated circuits Congresses |
| subject_GND | (DE-588)1071861417 |
| title | Proceedings of the IEEE 1993 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 9 - 12, 1993 |
| title_auth | Proceedings of the IEEE 1993 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 9 - 12, 1993 |
| title_exact_search | Proceedings of the IEEE 1993 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 9 - 12, 1993 |
| title_full | Proceedings of the IEEE 1993 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 9 - 12, 1993 |
| title_fullStr | Proceedings of the IEEE 1993 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 9 - 12, 1993 |
| title_full_unstemmed | Proceedings of the IEEE 1993 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 9 - 12, 1993 |
| title_short | Proceedings of the IEEE 1993 Custom Integrated Circuits Conference |
| title_sort | proceedings of the ieee 1993 custom integrated circuits conference town and country hotel san diego california may 9 12 1993 |
| title_sub | Town and Country Hotel, San Diego, California, May 9 - 12, 1993 |
| topic | Integrated circuits Congresses |
| topic_facet | Integrated circuits Congresses Konferenzschrift |
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