A survey on parallel logic simulation:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | Undetermined |
| Veröffentlicht: |
Saarbrücken
Univ. des Saarlandes
1993
|
| Schriftenreihe: | Sonderforschungsbereich VLSI-Entwurfsmethoden und Parallelität <Saarbrücken; Kaiserslautern>: SFB-Bericht
1993,14 |
| Beschreibung: | 45 S. |
Internformat
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Datensatz im Suchindex
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| any_adam_object | |
| author | Meister, Gerd |
| author_facet | Meister, Gerd |
| author_role | aut |
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| building | Verbundindex |
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| id | DE-604.BV010363237 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:51:11Z |
| institution | BVB |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006898264 |
| oclc_num | 634222852 |
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| physical | 45 S. |
| publishDate | 1993 |
| publishDateSearch | 1993 |
| publishDateSort | 1993 |
| publisher | Univ. des Saarlandes |
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| series | Sonderforschungsbereich VLSI-Entwurfsmethoden und Parallelität <Saarbrücken; Kaiserslautern>: SFB-Bericht |
| series2 | Sonderforschungsbereich VLSI-Entwurfsmethoden und Parallelität <Saarbrücken; Kaiserslautern>: SFB-Bericht |
| spelling | Meister, Gerd Verfasser aut A survey on parallel logic simulation Gerd Meister Saarbrücken Univ. des Saarlandes 1993 45 S. txt rdacontent n rdamedia nc rdacarrier Sonderforschungsbereich VLSI-Entwurfsmethoden und Parallelität <Saarbrücken; Kaiserslautern>: SFB-Bericht 1993,14 Sonderforschungsbereich VLSI-Entwurfsmethoden und Parallelität <Saarbrücken; Kaiserslautern>: SFB-Bericht 1993,14 (DE-604)BV006185478 1993,14 |
| spellingShingle | Meister, Gerd A survey on parallel logic simulation Sonderforschungsbereich VLSI-Entwurfsmethoden und Parallelität <Saarbrücken; Kaiserslautern>: SFB-Bericht |
| title | A survey on parallel logic simulation |
| title_auth | A survey on parallel logic simulation |
| title_exact_search | A survey on parallel logic simulation |
| title_full | A survey on parallel logic simulation Gerd Meister |
| title_fullStr | A survey on parallel logic simulation Gerd Meister |
| title_full_unstemmed | A survey on parallel logic simulation Gerd Meister |
| title_short | A survey on parallel logic simulation |
| title_sort | a survey on parallel logic simulation |
| volume_link | (DE-604)BV006185478 |
| work_keys_str_mv | AT meistergerd asurveyonparallellogicsimulation |