Algorithms and parallel VLSI architectures III: proceedings of the International Workshop Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29 - 31, 1994
Gespeichert in:
| Format: | Tagungsbericht Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Amsterdam u.a.
Elsevier
1995
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | X, 413 S. Ill., graph. Darst. |
| ISBN: | 0444821066 |
Internformat
MARC
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| 245 | 1 | 0 | |a Algorithms and parallel VLSI architectures III |b proceedings of the International Workshop Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29 - 31, 1994 |c ed. by Marc Moonen ... |
| 264 | 1 | |a Amsterdam u.a. |b Elsevier |c 1995 | |
| 300 | |a X, 413 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Computers - Design | |
| 650 | 4 | |a Computer algorithms |v Congresses | |
| 650 | 4 | |a Computer architecture |v Congresses | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |v Congresses | |
| 650 | 4 | |a Parallel processing (Electronic computers) |v Congresses | |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |2 gnd-content | |
| 700 | 1 | |a Moonen, Marc S. |e Sonstige |4 oth | |
| 711 | 2 | |a International Workshop on Algorithms and Parallel VLSI Architectures |n 3 |d 1994 |c Löwen |j Sonstige |0 (DE-588)5181883-8 |4 oth | |
| 856 | 4 | 2 | |m Digitalisierung TU Muenchen |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006895055&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-006895055 | |
Datensatz im Suchindex
| _version_ | 1820882555226816512 |
|---|---|
| adam_text |
TABLE
OF
CONTENTS
Introduction:
algorithms and parallel VLSI architectures
PART
1.
PARALLEL ALGORITHMS
1.
Subspace methods in system identification and source localization
P.A.
Regalia
13
2.
Pipelining the inverse updates RLS array by algorithmic engineering
J.G. McWhirter and I.E. Proudler
25
3.
Hierarchical signal flow graph representation of the square-root covariance
Kalman
filter
D. W. Brown and
F.M.F. Gaston
37
4.
A systolic algorithm for block-regularized RLS identification
J.
Schier
49
5.
Numerical analysis of a normalised RLS filter using a probability description
of propagated data
J. Kadlec
61
6.
Adaptive approximate rotations for computing the symmetric
EVD
J.
Götze
and G.J. Hekstra
73
7.
Parallel implementation of the double bracket matrix flow for eigenvalue-
eigenvector computation and sorting
JV. Saxena and J.J. Clark
85
8.
Parallel block iterative solvers for heterogeneous computing environments
M. Arioli, A.
Drummond,
I.S. Duff and D. Ruiz
97
9.
Efficient VLSI architecture for residue to binary converter
G.C. Cardarilli,
R. Lojacono,
M.
Re
and M.
Salerno
109
Table
of
Contents
PART
2. PARALLEL
ARCHITECTURES
10.
A case study in algorithm-architecture codesign: hardware-accelerator for
long integer arithmetic
С
Riem,
J.
König
and L.
Thiele 119
11.
An optimisation methodology for mapping a diffusion algorithm for vision
into a modular and flexible array architecture
J. Rosseel, F. Catthoor, T. Gijbels, P. Six, L. Van Goal and H.
De Man 131
12.
A scalable design for dictionary machines
T. Duboux,
A. Ferreira
and M.
Gastaldo 143
13.
Systolic implementation of Smith and Waterman algorithm on a SIMD
coprocessor
D. Archambaud, I.
Saraiva
Silva
and J.
Penné
155
14.
Architecture and programming of parallel video signal processors
K.
Vissers,
G.
Essink, P. van Gerwen, P.
Janssen,
О.
Popp,
E. Riddersma,
Ή.
Veendrick
167
15.
A
highly parallel single-chip
video
signal
processor
К.
Rönner, J. Kneip
and P.
Pirsch 179
16.
A memory efficient, programmable multi-processor architecture for real-time
motion estimation type algorithms
E. De
Greef, F. Catthoor and H.
De Man 191
17.
Instruction-level parallelism in asynchronous processor architectures
D.K. Arvind and V.E.F.
Rebelio
203
18.
High speed wood inspection using a parallel VLSI architecture
M. Hall and
A. Astrom
215
19.
CONVEX exemplar systems
:
scalable parallel processing
J. van Kats
227
Table
of Contents
20.
Modelling the 2-D FCT on a multiprocessor system
C.A. Christopoulos,
A.N.
Skodras and J. Cornells
235
21.
Parallel
grep
J.
Champeau,
L.
Le Pape and
В.
Pettier
245
PART
3.
PARALLEL COMPILATION
22.
Compiling for massively parallel architectures: a perspective
P. Feautrier
259
23.
DIV,
FLOOR, CEIL, MOD and STEP functions in nested loop programs
and linearly bounded lattices
P. Held and A.C.J. Kienhuis
271
24.
Uniformisation
techniques for reducible integral recurrence equations
L. Rapanotti and G.M. Megson
283
25.
HOPP
-
A higher-order parallel programming model
R. Rangaswami
295
26.
Design by transformation of synchronous descriptions
G. Durrieu and M. Lemaitre
307
27.
Heuristics for evaluation of array expressions on state of the art massively
parallel machines
V.
Bouchitté, P. Boulet,
A. Darte
and Y. Robert
319
28.
On factors limiting the generation of efficient compiler-parallelized programs
M.R. Werth and P. Feautrier
331
29.
From dependence analysis to communication code generation: the 'look
forwards' model
С
Reffay and G.-R. Perrin
341
Table of Contents
30.
Mapping complex image processing algorithms onto heterogeneous multi¬
processors regarding architecture dependent performance parameters
M. Schwiegershausen, M.
Schönfeld
and P.
Pirsch 353
31.
Optimal communication for a graph based DSP silicon compiler
H.-K. Kim
365
32.
Resource-constrained software pipelining for high-level synthesis of DSP
systems
F. Sanchez and J. Cortadella
377
33.
A portable
testbed
for evaluating different approaches to distributed logic
simulation
P. Luksch
389
34.
A simulator for optical parallel computer architectures
N.
Langloh, H. Sahli, A. Damianakis, M. Mertens and J. Cornells
401
Authors index
413 |
| any_adam_object | 1 |
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| discipline | Informatik |
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| language | English |
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| spelling | Algorithms and parallel VLSI architectures III proceedings of the International Workshop Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29 - 31, 1994 ed. by Marc Moonen ... Amsterdam u.a. Elsevier 1995 X, 413 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Computers - Design Computer algorithms Congresses Computer architecture Congresses Integrated circuits Very large scale integration Congresses Parallel processing (Electronic computers) Congresses (DE-588)1071861417 Konferenzschrift gnd-content Moonen, Marc S. Sonstige oth International Workshop on Algorithms and Parallel VLSI Architectures 3 1994 Löwen Sonstige (DE-588)5181883-8 oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006895055&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Algorithms and parallel VLSI architectures III proceedings of the International Workshop Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29 - 31, 1994 Computers - Design Computer algorithms Congresses Computer architecture Congresses Integrated circuits Very large scale integration Congresses Parallel processing (Electronic computers) Congresses |
| subject_GND | (DE-588)1071861417 |
| title | Algorithms and parallel VLSI architectures III proceedings of the International Workshop Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29 - 31, 1994 |
| title_auth | Algorithms and parallel VLSI architectures III proceedings of the International Workshop Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29 - 31, 1994 |
| title_exact_search | Algorithms and parallel VLSI architectures III proceedings of the International Workshop Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29 - 31, 1994 |
| title_full | Algorithms and parallel VLSI architectures III proceedings of the International Workshop Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29 - 31, 1994 ed. by Marc Moonen ... |
| title_fullStr | Algorithms and parallel VLSI architectures III proceedings of the International Workshop Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29 - 31, 1994 ed. by Marc Moonen ... |
| title_full_unstemmed | Algorithms and parallel VLSI architectures III proceedings of the International Workshop Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29 - 31, 1994 ed. by Marc Moonen ... |
| title_short | Algorithms and parallel VLSI architectures III |
| title_sort | algorithms and parallel vlsi architectures iii proceedings of the international workshop algorithms and parallel vlsi architectures iii leuven belgium august 29 31 1994 |
| title_sub | proceedings of the International Workshop Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29 - 31, 1994 |
| topic | Computers - Design Computer algorithms Congresses Computer architecture Congresses Integrated circuits Very large scale integration Congresses Parallel processing (Electronic computers) Congresses |
| topic_facet | Computers - Design Computer algorithms Congresses Computer architecture Congresses Integrated circuits Very large scale integration Congresses Parallel processing (Electronic computers) Congresses Konferenzschrift |
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