Proceedings: May 25 - 27, 1994, Boston, Massachusetts
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Los Alamitos, Calif. u.a.
IEEE Computer Soc. Press
1994
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XII, 368 S. Ill., graph. Darst. |
| ISBN: | 0818656506 0818656514 0818656522 |
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| 111 | 2 | |a International Symposium on Multiple Valued Logic |n 24 |d 1994 |c Boston, Mass. |j Verfasser |0 (DE-588)5125700-2 |4 aut | |
| 245 | 1 | 0 | |a Proceedings |b May 25 - 27, 1994, Boston, Massachusetts |c The twenty-fourth International Symposium on Multiple-Valued Logic |
| 264 | 1 | |a Los Alamitos, Calif. u.a. |b IEEE Computer Soc. Press |c 1994 | |
| 300 | |a XII, 368 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Logique multivalente - Congrès | |
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| 650 | 7 | |a circuit logique |2 inriac | |
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Datensatz im Suchindex
| _version_ | 1820882554218086400 |
|---|---|
| adam_text |
Contents
Message
from the
Symposium
Chair
.ix
Message
from the Program Chair
.
χ
Organizing Committee
.xi
Referees
.xii
Session
1:
Invited Address
Digital Circuit Verification using Partially-Ordered State Models.
Randal E. Bryant, Carnegie-Mellon Univ., U.S.A.
Carl-Johan H.
Seger,
University of British Columbia, Canada
Session 2a: Circuits I
CML Current Mode Full Adders for 2.5-V Power Supply
.10
A. Kazeminejad, K.
Navi,
and D. Etiemble
Quaternary Multiplier Circuit
.15
W.-S.
Chu
and W. Current
Multiple-Valued Current-Mode
MOS
Integrated Circuits Based on Dual-Rail
Source-Coupled Logic
.19
T. Hanyu, A. Mochizuki, and M. Kameyama
Performance of CMOS Current Mode Full Adders
.27
K.
Navi,
A. Kazeminejad, and D. Etiemble
Synthesis of
Multi-
Variable MVL Functions Using Hybrid Mode CMOS Logic
.35
Y.-J. Chang and C.L. Lee
Session 2b: Logic Design I
Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits
.44
H.M. Wang, C.L. Lee, and J.E. Chen
A Multiple-Valued Logic Synthesis using the Kleenean Coefficients
.52
Y.
Hata
and K. Yamato
Decomposition-Based Synthesis of Multiple-Valued Functions for Threshold Logic
Network Realization
.58
G.H.
Abdel-Hamid
and M.H. Abd-El-Barr
Efficient Graph Based Representation of
Multi-
Valued Functions with an Application to
Genetic Algorithms
.65
B. Becker and R.
Drechsler
Multiple-Valued Logic Operations with Universal Literals
.73
G.W. DueckandJ.T. Butler
Session 3a: Logic Design II
Calculation of Reed-Muller-Fourier Coefficients of Multiple-Valued Functions through
Multi-Place Decision Diagrams
.82
R.S. Stankovic', M. Stankovic',
С
Moraga,
and
T.
Sasao
Spectral Transformation
of
Multiple-
Valued Decision Diagrams
.89
D.M.
Miller
A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion
.97
T. Sasao andJ.T. Butler
Session 3b: Logic I
Lattices of Resolution Logics
.108
Z. Stachniak
Computing Prime Implicantsflmplicates for Regular Logics
.115
A. Ramesh and
N.
V. Murray
Minimization for Kleene-Stone Logic Functions
. 124
N.
Takagi, K. Nakashima, and M. Mukaidono
Session 4a: Fuzzy Logic, Applications, and Circuits
Parallel Processing of Fuzzy Inferences
.134
C.
Moraga,
J.
Cañas,
R.
Monge,
L.
Salinas,
and
M.
Gómez
On Scheduling in Multiprocessor Systems Using Fuzzy Logic
.141
A.S. Kaviani andZ.G. Vranesic
A Field Programmable Analog Array for Continuous, Fuzzy, and
Multi-
Valued
Logic Applications
.148
E.
Pierzchała,
M.A. Perkowski, and S. Grygiel
Multi-Peak Resonant Tunneling Diodes Based Fuzzifiers
.156
H. Tang, H.C. Lin, andS.J. Wei
Session 4b: Algebra I
Enumeration of Function and Bases of Three-Valued Set Logic under Compositions
with Boolean Functions
.164
J. Demetrovics, C. Reischer, D. Simovici, and I. Stojmenovic
Searching for Complete Functions over E(3) with Small Radii
.172
F.J. Cabrasawan and T.C. Wesselkamper
Completeness Criteria in Many-Valued Set Logic Under Compositions
with Boolean Functions
.177
/.
Stojmenovic
The Completeness Problem on the Product of Algebras of Finite-Valued Logic
.184
B.A. Romov
Session
5:
Invited Address
Resonant Tunneling Diodes for
Multi-
Valued Digital Applications
.188
H.C. Lin, Univ. of Maryland, U.S.A.
Session 6a: Circuits II
Interband-Tunneling III-V Semiconductor Structures for Multiple-Valued Literal
and Arithmetic Functions
.198
L.J. Micheel, H.L.
Hartnagel,
W.
T.
Anderson,
S.W. Kirchoefer,
and N.A. Papanicolaou
vi
Design
of Wave-Parallel Computing Circuits for Densely Connected Architectures
.207
Y. Ywninaka, T. Aoki, and T. Higuchi
Design of Multiwave Computing Circuits Based on a Model of Integrated
Opto-Electronic Devices
.215
Y. Watanabe, T. Aoki, and T. Higuchi
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations.
223
M. Nakajima and M. Kameyama
Design of Multiplex Interconnection Networks for Massively Parallel
Computing Systems
.231
T. Takimoto, T. Aoki, and T. Higuchi
Session 6b: Logic II
Efficient Deduction in Many-Valued Logics
.240
R. Hähnle
The Satisfiability Problem in Multiple-Valued Horn Formulae
.250
G. Escalada-lmaz and
F. Manyà
Approximating Propositional Calculi by Finite-Valued Logics
.257
M. Baaz and R.
Zach
On
Т
-Quantifiers and S-Quantifiers
.264
H.
Thiele
An Algebraic Method to Decide the Deduction Problem in Many-Valued
Propositional Calculus
.270
J.-Z. Wu and H.-Y. Tan
Session
7:
Invited Address
Soft Computing Perspective
.276
Elie
Sanchez,
Institut
Méditerranéen de Technologie, France
Session 8a: Logic Design
III
Full Sensitivity and Test Generation for Multiple-Valued Logic Circuits
.284
E.V.
Dubrova, D.B. Gurov, andJ.C. Muzio
Complete Test Set for Multiple-Valued Logic Networks
.289
H.M. Wang, C.L. Lee, andJ.E. Chen
Design of Fault-Tolerant Cellular Arrays on Multiple-Valued Logic
.297
N.
Kamiura, Y.
Hata,
and K. Yamato
Session 8b: Algebra II
Hereditary Clones of Multiple Valued Logic Algebra
.306
G. Pogosyan, A. Nozaki, M. Miyakawa, and
¡.G.
Rosenberg
Many-Valued Generalizations of Two Finite Intervals in Post's Lattice
.314
G.C. Denham
Several Remarks on Algebraic Entropy
.319
C. Reischer, D. Simovici, and I. Stojmenovic
vii
Session 9a: Logic Design
IV
Identification
of
Linear
Ternary
Logic
Functions and its Algorithms.
324
В.
Fei,
Q.
Hong, and G.
Zhang
Knot Automata
.328
LH.
Kauffman
Multiple-Valued-Input
TANT
Networks
.334
M.A. Perkowski and M.
Chrzanów
ska-J
e
ske
Multiple-Valued Combinational Circuits with Feedback
.342
J.T. Butler and T. Sasao
Session 9b: Logic III
On Multiple-Valued Separable Unordered Codes
.350
Y. Nagata and M. Mukaidono
A Weak Propositional Calculus for Signal Processing with Thresholds
.356
G. Epstein
A Four-Valued Logic and Switch-Level Differences
.362
M.
Ни
Author Index
.368
vin |
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| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Mathematik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre_facet | Konferenzschrift 1994 Boston Mass. |
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| illustrated | Illustrated |
| indexdate | 2025-01-10T17:08:44Z |
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| isbn | 0818656506 0818656514 0818656522 |
| language | English |
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| spelling | International Symposium on Multiple Valued Logic 24 1994 Boston, Mass. Verfasser (DE-588)5125700-2 aut Proceedings May 25 - 27, 1994, Boston, Massachusetts The twenty-fourth International Symposium on Multiple-Valued Logic Los Alamitos, Calif. u.a. IEEE Computer Soc. Press 1994 XII, 368 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Logique multivalente - Congrès Logique multivalente - Congrès ram algebre inriac circuit logique inriac logique floue inriac logique multivaluee inriac logique inriac structure logique inriac Many-valued logic Congresses Mehrwertige Logik (DE-588)4169335-8 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1994 Boston Mass. gnd-content Mehrwertige Logik (DE-588)4169335-8 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006770674&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings May 25 - 27, 1994, Boston, Massachusetts Logique multivalente - Congrès Logique multivalente - Congrès ram algebre inriac circuit logique inriac logique floue inriac logique multivaluee inriac logique inriac structure logique inriac Many-valued logic Congresses Mehrwertige Logik (DE-588)4169335-8 gnd |
| subject_GND | (DE-588)4169335-8 (DE-588)1071861417 |
| title | Proceedings May 25 - 27, 1994, Boston, Massachusetts |
| title_auth | Proceedings May 25 - 27, 1994, Boston, Massachusetts |
| title_exact_search | Proceedings May 25 - 27, 1994, Boston, Massachusetts |
| title_full | Proceedings May 25 - 27, 1994, Boston, Massachusetts The twenty-fourth International Symposium on Multiple-Valued Logic |
| title_fullStr | Proceedings May 25 - 27, 1994, Boston, Massachusetts The twenty-fourth International Symposium on Multiple-Valued Logic |
| title_full_unstemmed | Proceedings May 25 - 27, 1994, Boston, Massachusetts The twenty-fourth International Symposium on Multiple-Valued Logic |
| title_short | Proceedings |
| title_sort | proceedings may 25 27 1994 boston massachusetts |
| title_sub | May 25 - 27, 1994, Boston, Massachusetts |
| topic | Logique multivalente - Congrès Logique multivalente - Congrès ram algebre inriac circuit logique inriac logique floue inriac logique multivaluee inriac logique inriac structure logique inriac Many-valued logic Congresses Mehrwertige Logik (DE-588)4169335-8 gnd |
| topic_facet | Logique multivalente - Congrès algebre circuit logique logique floue logique multivaluee logique structure logique Many-valued logic Congresses Mehrwertige Logik Konferenzschrift 1994 Boston Mass. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006770674&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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