MIPS, a VLSI processor architecture:
MIPS is a new single chip VLSI processor architecture. It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. Software solutions to several traditional hardwar...
Gespeichert in:
| Format: | Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Stanford, CA
1981
|
| Schriftenreihe: | Computer Systems Laboratory <Stanford, Calif.>: Technical report
223 |
| Schlagworte: | |
| Zusammenfassung: | MIPS is a new single chip VLSI processor architecture. It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. Software solutions to several traditional hardware problems, such as providing pipeline interlocks, are used. |
| Beschreibung: | 11 S. |
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| id | DE-604.BV010046851 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:45:33Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006664020 |
| oclc_num | 80148231 |
| open_access_boolean | |
| physical | 11 S. |
| publishDate | 1981 |
| publishDateSearch | 1981 |
| publishDateSort | 1981 |
| record_format | marc |
| series | Computer Systems Laboratory <Stanford, Calif.>: Technical report |
| series2 | Computer Systems Laboratory <Stanford, Calif.>: Technical report |
| spelling | MIPS, a VLSI processor architecture John Hennessy ... Stanford, CA 1981 11 S. txt rdacontent n rdamedia nc rdacarrier Computer Systems Laboratory <Stanford, Calif.>: Technical report 223 MIPS is a new single chip VLSI processor architecture. It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. Software solutions to several traditional hardware problems, such as providing pipeline interlocks, are used. Computer architecture Computers, Pipeline Integrated circuits Very large scale integration Microprocessors Hennessy, John Sonstige oth Computer Systems Laboratory <Stanford, Calif.>: Technical report 223 (DE-604)BV001897278 223 |
| spellingShingle | MIPS, a VLSI processor architecture Computer Systems Laboratory <Stanford, Calif.>: Technical report Computer architecture Computers, Pipeline Integrated circuits Very large scale integration Microprocessors |
| title | MIPS, a VLSI processor architecture |
| title_auth | MIPS, a VLSI processor architecture |
| title_exact_search | MIPS, a VLSI processor architecture |
| title_full | MIPS, a VLSI processor architecture John Hennessy ... |
| title_fullStr | MIPS, a VLSI processor architecture John Hennessy ... |
| title_full_unstemmed | MIPS, a VLSI processor architecture John Hennessy ... |
| title_short | MIPS, a VLSI processor architecture |
| title_sort | mips a vlsi processor architecture |
| topic | Computer architecture Computers, Pipeline Integrated circuits Very large scale integration Microprocessors |
| topic_facet | Computer architecture Computers, Pipeline Integrated circuits Very large scale integration Microprocessors |
| volume_link | (DE-604)BV001897278 |
| work_keys_str_mv | AT hennessyjohn mipsavlsiprocessorarchitecture |