Proceedings: [October 2 - 6, 1994, Sheraton Washington Hotel, Washington, DC, USA ; test: the next 25 years]
Saved in:
| Corporate Author: | |
|---|---|
| Format: | Conference Proceeding Book |
| Language: | Undetermined |
| Published: |
LosAlamitos, CA
IEEE Computer Soc. Press
1994
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XII, 1033 S. Ill., graph. Darst. |
| ISBN: | 0780321022 0780321030 0780321049 |
Staff View
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| 300 | |a XII, 1033 S. |b Ill., graph. Darst. | ||
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Record in the Search Index
| _version_ | 1820882549270904832 |
|---|---|
| adam_text |
INTRODUCTORY SECTION
Welcoming Message
.1
Steering Committee
.2
Technical Program Committee
.4
Technical Papers Evaluation and Selection Process
.8
1995
Call for Papers
.9
1993
Paper Awards
.10
Reviewers
.1025
Author Index
.1031
SESSIONI:
PLENARY
John Masciola, Session Chair; Gerald Gordon, Moderator
Invited Address:
A Test Retrospection and a Quest for Direction
Robert E. Anderson
.11
Keynote Address:
Test: The New Value-Added Field
Aart
J.
de Geus.
12
Invited Address:
Faster, Better, Cheaper: What Does This Mean For The Test
Industry?
Walt Wilson
.13
SESSION
2:
KNOWN-GOOD-DIE IMPACT ON
MCM
TESTING
D. Keezer, Session Chair: W. Mann, Coordinator
2.1
Development of a Solution for Achieving Known-Good-Die
L. Prokopchak
.15
2.2
Membrane Probe Technology for
MCM
Known-Good-Die
T. Ueno, Y. Kondoh
.22
2.3
High-Yield Multichip Modules Based on Minimal
1С
Pretest
W. Burdick, W.
Daum.30
2.4
Feasibility Study of Smart Substrate Multichip Modules
A. Gattiker, W. Maly
.41
SESSION
3:
MICROPROCESSOR TEST
D.
Josephson,
Session Chair; G. Giles, Coordinator
3.1
Testability Strategy of the ALPHA
AXP
21164
Micropro¬
cessor
D. Bhavsar. J. Edmondson
.50
3.2
Testability Features of the MC68060 Microprocessor
A. Crouch, M. Pressly, J. Circello
.60
3.3
microSPARCftm): A Case Study of Scan-Based Debug
K. Holdbrook, S. Joshi,
S. Mitra, J.
Petotino, R. Raman,
M.Wong
.70
3.4
Balancing Structured and Ad-hoc Design for Test: Test¬
ing of the PowerPC 603(tm) Microprocessor
C. Hunter, K. VWa-Torku, J. LeBlanc
.76
Table of
Contents
ITC
Office
205
Tennyson Avenue, Suite
С
Altoona, PA
16602
USA
Tel: (814) 941-4666
III
INTERNATIONAL
TEST
CONFERENCE
1994
SESSION
4:
TEST STRATEGY AND THE BOTTOM LINE
J. Hughes, Session Chair; B. West, Coordinator
4.1
System Test Cost Modelling Based on Event Rate Analysis
D. Farren, A. Ambler
.84
4.2
ASIC Test Cost/Strategy Trade-offs
D. Wheater, P. Nigh, J. Trinko Mechler, L.
Lacroix
.93
4.3
A Test Process Optimization and Cost Modeling Tool
T.Moore
.103
4.4
When Does It Make
φ
to Give Up Physical Test Access?
D. Greene
.111
SESSION
5:
STRUCTURED METHODOLOGIES FOR SYSTEM TEST
R. Campbell, Session Chair;
N.
Jarwala, Coordinator
5.1
3B21D BIST/Boundary-Scan System Diagnostic Test
Story, E. Behnke
.120
5.2
Modeling for Structured System Interconnect Test
F. Angelotti
.127
5.3
System-Level Testability of Hardware/Software Systems
H. Vranken, M. Stevens, M.
Segers,
J. van Rhee
.134
5.4
A Generic Test and Maintenance Node for Embedded
System Test, J. Lofgren
.143
SESSION
6:
DELAY TESTING AND SYNTHESIS
I. Pomeranz, Session Chair; K. Cheng and J.
Rajski,
Coordinators
6.1
Fastpath: A Path-Delay Test Generator for Standard
Scan Designs, B. Underwood, W. Law, S. Kang, H. Konuk
.154
6.2
On Path-Delay Testing in a Standard Scan Environment
P.
Varma
.164
6.3
Automated Logic Synthesis of Random-Pattern-Testable
Circuits,
N.
Touba, E. McCluskey
.174
6.4
Transfonning Behavioral Specifications to Facilitate
Synthesis of Testable Designs,
S. Dey, M.
Potkonjak
.184
SESSION
7:
PAVING THE SUPERHIGHWAY TO ULTIMATE CMOS
1С
QUALITY, P. Maxwell, Session Chair; J. Soden, Coordinator
7.1
QTAG: A Standard for Test Fixture Based
Ι^ς/Ι^
Monitors, K. Baker
.194
7.2
An Off-chip IDDQ Current Measurement Unit for
Telecommunication ASICs
H. Manhaeve, P. Wrighton, J. van
Sas, U.
Swerts
.203
7.3
Development of a CLASS
1
QTAG Monitor
K. Baker,
A. Bratt,
A. Richardson, A. Welbers
.213
7.4
A Serially Addressable, Flexible Current Monitor for Test
Fixture Based
l^^
Testing
A. Hales
.223
iv
SESSION 8:
SEQUENTIAL TEST
GENERATION
J.
Lee, Session
Chair; S. Davidson,
Coordinator
8.1
On
the Initialization of Sequential Circuits
J. Wehbeh, D. Saab
.233
8.2
An Automatic Test Pattern Generator for Large Sequential
Circuits Based on Genetic Algorithms
P. Prinetto, M. Rebaudengo, M. Sonza
Reorda
.240
8.3
ATPG for Heat Dissipation Minimization During Test
Application,
S. Wang, S.
Gupta
.250
8.4
Sequentially Untestable Faults Identified Without Search
("Simple Implications Beat Exhaustive Search!")
M. Iyer, M. Abramovici
.259
SESSION
9:
ATE TOPICS
S. O'Keefe, Session Chair; D. Wheater, Coordinator
9.1
Implementation of a Dual-Segment Architecture for a High-
Pin-Count VLSI Test System, M. Davis
.267
9.2
500-MHz Testing on a 100-MHz Tester
D. Wimmers, K. Sakaitani, B. West
.273
9.3
Modeling the Effect of Ground Bounce on Noise Margin
M. Haydt, R. Owens, S. Mourad
.279
9.4
Modular Mixed Signal Testing: High Speed or High
Resolution, E. Kushnick
.286
SESSION
10:
SYSTEM-LEVEL APPLICATIONS OF BIST,
BOUNDARY-SCAN, DFT, K. Roy, Session Chair,
K. Kornegay, Coordinator
10.1
Built-in System Test and Fault Location
G. McLeod
.291
10.2
Roadmap for Extending IEEE
1149.1
for Hierarchical
Control of Locally-Stored, Standardized-Command-Set
Test Programs, J. Andrews
.300
10.3
Environmental Stress Testing with Boundary-Scan
D. Le,
I. Karolik, R. Smith, A. Mcgovern,
С
Curette, J. Ulbin,
M. Zarubaiko, C. Henry,
L
Stevens
.307
10.4
An Approach to Accelerate Scan Testing in IEEE
1149.1
Architectures. L. Whetsel
.314
SESSION
11:
DFT BY CLOCK MANIPULATION
S. Kundu, Session Chair; D. Bhavsar, Coordinator
11.1
Multi-Frequency, Multi-Phase Scan Chain
K. Kim,
L
Schultz.323
11.2
A Test-Clock Reduction Method for Scan-Designed
Circuits, J. Chang,
C. Lin
.331
11.3
Hybrid Design for Testability Combining Scan and Clock
Line Control and Method for Test Generation
S. Baeg, W. Rogers
.340
11.4
In-System Timing Extraction and Control Through Scan-
Based, Test-Access Ports, A. DeHon
.350
Table of
Contents
INTERNATIONAL
TEST CONFERENCE
1994
SESSION 12 - PANEL: "SO
YOU
STILL
DON'T THINK YOU NEED TO
TEST?"
T. Ambler, S. Szygenda, Co-moderators; T. Ambler, Organizer
SESSION
13 -
PANEL: TESTING HIGH-SPEED
DRAMs
G.
Watkins, Moderator; T. Tokuno, Organizer
13.1
Testing 256k Word
χ
16
Bit Cache DRAM (CDRAM)
Y. Konishi, T. Ogawa, M.Kumanoya
.360
13.2
Testing High Speed Drams
J. Gasbarro
.361
13.3
Practical Test Methods for Verification of the EDRAM
K. Stalnaker
.362
13.4
Testing Issues on High Speed Synchronous
DRAMs
W.
Lee
.363
SESSION
14 -
PANEL: BENCHMARKING TEST TOOLS
-
ARE THEY
NECESSARY AND WHY
R. Chandramouli, Moderator and Organizer
14.1
Benchmarking
K. Ruparel
.364
14.2
Potential Solutions for Benchmarking Issues
D. Sterba
.365
SESSION
15 -
PANEL:
MCM
TESTING: IS IT BOARD TEST OR
1С
TEST? Y. Zorian, Moderator; W. Mann, Organizer
15.1
Multichip Module Testing Methodologies: What's In;
What's Not, K. Posse
.366
15.2
MCM
Test Trade-Offs
J. Eastman
.367
SESSION
16 -
PANEL: SOUTHWEST TEST WORKSHOP
-
WAFER-
LEVEL TESTING, W. Mann, Moderator and Organizer
SESSION
17:
APPLICATIONS OF MEMORY BIST, Y. El-Ziq,
Session Chair; B. Nadeau-Dostie and K. Wagner, Coordinators
17.1
Aliasing-free Signature Analysis for RAM BIST
V. Yarmolik, M. Nicolaidis, O. Kebichi
.368
17.2
An Effective BIST Scheme for Ring-Address Type FIFOs
Y. Zorian, A. van
de Goor,
I.
Schanstra.
378
17.3
The PowerPC603(tm) Microprocessor: An Array Built-in
Self-Test Mechanism
C. Hunter, J. Slaton, J.
Eno,
R. Jessani, C. Dietz
.388
SESSION
18:
TEST STRATEGIES FOR CMOS ICs
R. Aitken, Session Chair; R. Gulati, Coordinator
18.1
Testing CMOS Logic Gates for Realistic Shorts
B. Chess,
A. Freitas,
F.
Ferguson,
T. Larrabee
.395
18.2
Л
Study of IDDQ Subset Selection Algorithms for Bndging
Faults, S. Chakravarty, P. Thadikaran
.403
vi
18.3
Defect Classes
-
An Overdue Paradigm for CMOS
1С
Testing,
С
Hawkins, J. Soden, A. Righter, F. Ferguson
.413
SESSION
19:
MCM
TEST STRATEGIES
K. Posse, Chair; W. Mann, Coordinator
19.1
A Test Methodology to Support an
ASEM MCM
Foundry
T.
Storey,
С.
Lapihuska,
E.
Atwood,
L.
Su
.426
19.2
Test Strategies for a Family of Complex MCMs
A.Flint
.436
19.3
Designing "Dual-Personality" IEEE
1149.1
-Compliant
Multi-Chip Modules,
N.
Jarwala
.446
SESSION
20:
TEST ENGINEERING ACCURACY
S. Raissi, Session Chair; A. Downey, Coordinator
20.1
A Case Study in the Use of Scan in microSparcftm)
Testing and Debug, J. Katz
.456
20.2
A Hierarchical Environment for Interactive Test Engineering
T. Burch, J.
Hartmann, G.
Hotz,
M.
Krallmann, U. Nikolaus,
S. Reddy,
U.
Sparmann.461
20.3
Ensuring System Traceability to International Standards
S.Max
.471
SESSION
21:
HARDWARE PATTERN GENERATION AND
COMPRESSION,
A. Ivanov,
Session Chair; B. Nadeau-Dostie
and K. Wagner, Coordinators
21.1
GLFSR
-
A New Test Pattern Generator for Built-in Self-
Test, D. Pradhan, M. Chatterjee
.481
21.2
Design of an Efficient Weighted-Random-Pattem
Generation System
R. Kapur, S.
Patii,
T.
Snethen,
T.
Williams
.491
21.3
Efficient Test-Response Compression for Multiple-Output
Circuits, K. Chakrabarty, J. Hayes
.501
SESSION
22:
PRACTICAL MEMORY TESTING
B. Cockburn, Session Chair; T. Furuyama, Coordinator
22.1
ECC-On-SIMM Test Challenges
T. Dell
.511
22.2
Techniques for Characterizing
DRAMs
With a 500-MHz
Interface, J. Gasbarro, M. Horowitz
.516
22.3
Automatic Failure-Analysis System for High-Density
DRAM, S. Oh, J. Kim, H. Choi, S. Choi, K. Park,
J. Park, W. Lee
.526
SESSION
23:
THE TEST ENGINEER'S ROLE IN.
N.
Donlin, Session Chair; E.
Hnátek,
Coordinator
23.1 . 1С
TEST: Detection and Correction of Systematic Type
1
Test Errors Through Concurrent
Engineering
В.
Kosar.
531
Table of
Contents
VII
INTERNATIONAL
TEST CONFERENCE
1994
23.2 . BOARD TEST:
Defects,
Fault
Coverage, Yield and
Cost in Board Manufacturing
M. Tegethoff, T. Chen
.539
23.3 .
SYSTEM TEST; HALT: Bridging the Gap Between
Theory and Practice,
С
Ascarrunz
.548
SESSION
24:
DEFECT, QUALITY, AND COST CONCERNS FOR
CMOS ICs, S. Dikic, Session Chair; J. Soden, Coordinator
24.1
Residual Charge on the Faulty Floating Gate
MOS
Transistor, S. Johnson
.555
24.2
Variable Supply Voltage Testing for Analogue CMOS
and Bipolar Circuits,
E. Bruis
.562
24.3
Is
lnn„
Yield Loss Inevitable?
S. Davidson
.572
SESSION
25:
SOFTWARE ENVIRONMENTS FOR ATE
A. Downey, Session Chair and Coordinator
25.1
A Software Architecture for Mixed-Signal Functional
Testing, J. Masciola, G. Morgan,
G. Templeton
.580
25.2
A Procedural Interface to Test
G. Maston
.587
25.3
An Intelligent Software-Integrated Environment of
1С
Testing, Y. Sun, X. Wang, W. Shi
.594
SESSION
26:
REAL FAULT SIMULATION FOR REAL CIRCUITS
L.
Baranyai,
Session Chair; S. Davidson, Coordinator
26.1
Parallel Pattern Fast Fault Simulation for Three-State
Circuits and Bidirectional I/O
J. van
der
Linden, M.
Konijnenburg,
A. van
de Goor.
604
26.2
A Hybrid Fault Simulator for Synchronous Sequential
Circuits, R.
Krieger,
В.
Becker,
M.
Keim.614
26.3
Reduced Scan Shift: A New Testing Method for Sequential
Circuit, Y. Higami, S. Kajihara, K. Kinoshita
.624
SESSION
27:
DESIGN FOR TEST CONSIDERATIONS FOR MIXED-
SIGNAL DEVICES
S. Kumar, Session Chair; R. Kramer and S. Kumar, Coordinators
27.1
An Integrated Approach for Analog Circuit Testing with a
Minimum Number of Detected Parameters
M.
Slamani,
B. Kaminska, G. Quesnel
.631
27.2
Analogue
Fault
Simulation
Based on Layout-Dependent
Fault Models
R.
Harvey, A. Richardson,
Ε.
Bruis,
К.
Baker
.641
27.3
An Analog Multi-Tone Signal Generator for Built-in
Self-Test Applications,
A. Lu, G.
Roberts
.650
SESSION
28:
BOUNDARY SCAN DESIGN TECHNIQUES
D. Chiles, Session Chair; J. Beausang, Coordinator
28.1
Low-Power Mode and IEEE
1149.1
Compliance
-
A
Low-Power Solution, A. Crouch,
R. Rámus, C
Maunder
.660
VIII
28.2
An IDDQ Based Built-in Concurrent Test Technique for
Interconnects in a Boundary-Scan Environment
С
Su,
К.
Hwang,
S.
Jou
.670
28.3
Fault Injection Boundary-Scan Design for Verification of
Fault-Tolerant Systems, S. Chau
.677
SESSION
29:
ATE PIN ELECTRONICS, TIMING, AND ACCURACY
J. Woyke, Session Chair; D. Wheater, Coordinator
29.1
Ultra Hi-Speed Pin-Electronics and Test Station Using
GaAs
1С,
T. Sekino, T. Okayasu
.683
29.2
Achieving ±30ps Accuracy in the
A TE
Environment
D. Petrich
.691
29.3
A Test-System Architecture to Reduce Transmission Line
Effects During High-Speed Testing
M. Mydill
.701
29.4
Application of Optoelectronic Techniques to High Speed
Testing, E. Sokolowska,
B. Kaminska
.710
SESSION
30:
TOWARDS QUANTIFYING DEFECT COVERAGE
S. Midkiff, Session Chair; R. Gulati, Coordinator
30.1
Back Annotation of Physical Defects into Gate-Level,
Realistic Faults in Digital ICs, M.
Calha,
M.
Santos,
F.
Gonçalves,
I.
Teixeira, J. Teixeira
.720
30.2
Simulation Results of an Efficient Defect-Analysis
Procedure, O. Stern, H.
Wunderlich.729
30.3
The Effect on Quality of Non-Uniform Fault Coverage and
Fault Probability, P. Maxwell, R. Aitken, L.
Huisman
.739
SESSION
31:
NEW TEST TECHNIQUE DEVELOPMENTS FOR
MIXED SIGNAL DEVICES, K.
Lanier,
Session Chair; R. Kramer
and S. Kumar, Coordinators
31.1
Application of Joint Time-Frequency Analysis in Mixed-
Signal Testing,
F. Bouwman,
T. Zwemstra, S. Hartanto,
К.
Baker,
J.
Koopmans
.747
31.2
Digitizer Error Extraction in the Nonlinearity Test
L. Hsieh, S. Kumar
.757
31.3
An Improved Method of ADC Jitter Measurement
Y. Langard, J.
Balat,
J.
Durand
.763
SESSION
32:
TEST DATA SYSTEMS, TEAMS, AND RESULTS
P. Mullenix, Session Chair; A. Miller, Coordinator
32.1
An On-Line Data Collection and Analysis System for VLSI
Devices at Wafer Probe and Final Test
G. Papadeas, D. Gauthier
.771
32.2
Test Station Workcell Controller and Resource
Relationship Design, S. Erjavic
.781
32.3
Calculating Error of Measurement on High-Speed
Microprocessor Test
T. Comard, M. Joshi, D. Morin, K. Sprague
.793
Table of
Contents
IX
INTERNATIONAL
TEST CONFERENCE
1994
SESSION 33:
EFFECTIVE BOARD-LEVEL TEST VECTOR
GENERATION, S. Oresjo, Session
Chair; D. Greene, Coordinator
33.1
Goal-Directed Vector Generation Using Sample ICs
D. Raymond, P. Stringer, H. Ng, M. Mitsumata,
B. Burk
.802
33.2
NAND
Trees Accurately Diagnose Board-Level Pin Faults
G. Robinson
.811
33.3
Non-Volatile Programmable Devices and In-Circuit Test
D. Raymond, D. Haigh,
R. Bodiek,
В.
Ryan,
D.
McCombs
.817
SESSION 34: SOFTWARE
TESTING
TOOLS
R.
McNitt, Coordinator
34.1
A Practical System for Mutation Testing: Help for the
Common Programmer, A. Offutt
.824
34.2
Improving Software Testability with
Asseđion
Insertion
H. Yin, J. Bieman
.831
34.3
Sleuth: A Domain-Based Testing Tool
A.
von
Mayrhauser, J. Walls,
R. Mraz
.840
SESSION
35:
MEMORY TEST ALGORITHMS
B. Cockburn, Session Chair; T. Furuyama, Coordinator
35.1
Efficient O(<n)BIST Algorithms for DDNPS Faults in
Dual-Port Memories
A. Amin,
M. Osman,
R.
Abdel-Aal,
H.
Al-Muhtaseb.850
35.2
Transparent Memory
Testing for Pattern-Sensitive Faults
M. Karpovsky, V. Yarmolik
.860
35.3
Generating March Tests Automatically
A. van
de Goor,
B. Smit
.870
SESSION
36:
DFT
IN PRACTICE
M.
Abadir, Session Chair, D. Bhavsar, Coordinator
36.1
Concurrent Engineering with DFT in the Digital System:
A Parallel Process, R. Sanchez
.879
36.2
Do You Practice Safe Test? What We Found Out About
Your Habits, C. Dean, Y. Zorian
.887
36.3
Control Strategies for Chip-Based DFT/BIST Hardware
D. Mukherjee, M. Pedram, M.
Breuer.893
SESSION
37:
BOARD TEST OPPORTUNITIES AND SOLUTIONS
С
Yau, Session Chair; D. Greene, Coordinator
37.1
Manufacturing-Test Simulator: A Concurrent-Engineering
Tool for Boards and MCMs
M. Tegethoff, T. Chen
.903
37.2
Testing Two Generations of HDTV Decoders-The Impact
of Boundary-Scan, L. Eerenstein
.911
37.3
Structure and Metrology for a Single-wire Analog
Testability Bus,
Y. Lu,
W.
Mao,
R. Dandapani, R. Gulati
.919
SESSION 38: INNOVATION IN LOGIC BIST, B. Koenemann,
Session
Chair;
К.
Wagner &
В.
Nadeau-Dostie,
Coordinators
38.1
Fixed-Biased Pseudorandom Built-in Self-Test for
Random-Pattern-Resistant Circuits
M. AlShaibi,
С
Kime.
929
38.2
Configuring
Flip-Flops
to BIS
Τ
Registers
A. Stroele, H.
Wunderlich.939
38.3
Making the Circular Self-Test Path Technique Effective for
Real Circuits, F.
Corno,
P. Prinetto, M. Sonza
Reorda
.949
SESSION
39:
HIGH-LEVEL TEST GENERATION
J. Abraham, Session Chair; S. Davidson, Coordinator
39.1
Behavioral-Test Generation using Mixed-Integer
Non-linear Programming, R. Ramchandani, D. Thomas
.958
39.2
B-algorithm: A Behavioral-Test Generation Algorithm
С
Cho, J. Armstrong
.968
39.3
Full-Symbolic A TPG for Large Circuits
G. Cabodi, P. Camurati, S.
Quer.980
SESSION
40:
TEST-SYNTHESIS PRACTICES
S. Kadkade, Session Chair; K. Cheng, Coordinator
40.1
On Synthesizing Circuits With Implicit Testability
Constraints, H. Cox
.989
40.2
A Simulation-Based Protocol-Driven Scan-Test-Design
Rule Checker, E. Pitty, D. Martin, H. Ma
.999
40.3
On Achieving Complete Testability of Synchronous
Sequential Circuits with Synchronizing Sequences
I. Pomeranz, S. Reddy
.1007
SESSION
41 -
PANEL: TESTERS AND TESTING IN THE NEXT TEN
YEARS, K. Baker, Moderator; B. West, Organizer
41.1
Integration of Design, Manufacturing and Testing
W. Maly
.1017
SESSION
42 -
PANEL: HOW CAN I DESIGN A TESTABLE MONSTER
CHIP?, R. Aiken, Moderator; G. Robinson, Organizer
SESSION
43 -
PANEL: WHICH BACKPLANE TEST INTERFACES
SHOULD I USE?,
С
Hudson, Moderator; P. McHugh, Organizer
43.1
Navigating Test Access In Systems
L. Whetsel
.1018
43.2
Using SCAN(tm) Bridge as an IEEE
1149.1
Protocol
Addressable, Multi-Drop, Backplane Test Bus
J. Andrews
.1019
43.3
Tihe
IEEE P1149.5 MTM-Bus, A Backplane Test and
Initialization Interface, P. McHugh
.1020
43.4
Backplane Test Bus Selection Criteria
С
Champlin
.1021
Table of
Contents
XI
INTERNATIONAL
TEST CONFERENCE
1994
43.5 1149.1
Scan Control Transport Levels
R. Gage
.1022
SESSION
44 -
PANEL: BOUNDARY SCAN: IT IS TIME TO GO
BEYOND ITS BOUNDARIES
R. Mercer, Moderator; B. Dervisoglu, Organizer
44.1
Observations on the 1149.x Family of Standards
K. Parker
.1023
44.2
Optimizing Boundary Scan in a Proprietary Environment
W. Eklow
.1024
Reviewers
.1025
Author Index
.1031
XII |
| any_adam_object | 1 |
| author_corporate | International Test Conference Washington, DC |
| author_corporate_role | aut |
| author_facet | International Test Conference Washington, DC |
| author_sort | International Test Conference Washington, DC |
| building | Verbundindex |
| bvnumber | BV009928961 |
| classification_rvk | ZN 4030 |
| classification_tum | DAT 330f |
| ctrlnum | (OCoLC)632368230 (DE-599)BVBBV009928961 |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre_facet | Konferenzschrift 1994 Washington DC |
| id | DE-604.BV009928961 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T17:08:39Z |
| institution | BVB |
| institution_GND | (DE-588)5130843-5 |
| isbn | 0780321022 0780321030 0780321049 |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006577094 |
| oclc_num | 632368230 |
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| physical | XII, 1033 S. Ill., graph. Darst. |
| publishDate | 1994 |
| publishDateSearch | 1994 |
| publishDateSort | 1994 |
| publisher | IEEE Computer Soc. Press |
| record_format | marc |
| spelling | International Test Conference 25 1994 Washington, DC Verfasser (DE-588)5130843-5 aut Proceedings [October 2 - 6, 1994, Sheraton Washington Hotel, Washington, DC, USA ; test: the next 25 years] International Test Conference 1994 LosAlamitos, CA IEEE Computer Soc. Press 1994 XII, 1033 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Mikroelektronik (DE-588)4039207-7 gnd rswk-swf Bildverstehen (DE-588)4202022-0 gnd rswk-swf Testen (DE-588)4367264-4 gnd rswk-swf Elektronik (DE-588)4014346-6 gnd rswk-swf Computerunterstütztes Verfahren (DE-588)4139030-1 gnd rswk-swf Computersimulation (DE-588)4148259-1 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Maschinelles Sehen (DE-588)4129594-8 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Test (DE-588)4059549-3 gnd rswk-swf Datenverarbeitungssystem (DE-588)4125229-9 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Telekommunikation (DE-588)4059360-5 gnd rswk-swf Medizin (DE-588)4038243-6 gnd rswk-swf Prüftechnik (DE-588)4047610-8 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1994 Washington DC gnd-content Test (DE-588)4059549-3 s DE-604 Integrierte Schaltung (DE-588)4027242-4 s Prüftechnik (DE-588)4047610-8 s 1\p DE-604 Datenverarbeitungssystem (DE-588)4125229-9 s Computersimulation (DE-588)4148259-1 s 2\p DE-604 Telekommunikation (DE-588)4059360-5 s 3\p DE-604 Mikroelektronik (DE-588)4039207-7 s 4\p DE-604 Elektronik (DE-588)4014346-6 s Testen (DE-588)4367264-4 s 5\p DE-604 VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s 6\p DE-604 Computerunterstütztes Verfahren (DE-588)4139030-1 s Medizin (DE-588)4038243-6 s 7\p DE-604 8\p DE-604 Bildverstehen (DE-588)4202022-0 s Maschinelles Sehen (DE-588)4129594-8 s 9\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006577094&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 5\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 6\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 7\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 8\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 9\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Proceedings [October 2 - 6, 1994, Sheraton Washington Hotel, Washington, DC, USA ; test: the next 25 years] Mikroelektronik (DE-588)4039207-7 gnd Bildverstehen (DE-588)4202022-0 gnd Testen (DE-588)4367264-4 gnd Elektronik (DE-588)4014346-6 gnd Computerunterstütztes Verfahren (DE-588)4139030-1 gnd Computersimulation (DE-588)4148259-1 gnd Entwurf (DE-588)4121208-3 gnd Maschinelles Sehen (DE-588)4129594-8 gnd VLSI (DE-588)4117388-0 gnd Test (DE-588)4059549-3 gnd Datenverarbeitungssystem (DE-588)4125229-9 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Telekommunikation (DE-588)4059360-5 gnd Medizin (DE-588)4038243-6 gnd Prüftechnik (DE-588)4047610-8 gnd |
| subject_GND | (DE-588)4039207-7 (DE-588)4202022-0 (DE-588)4367264-4 (DE-588)4014346-6 (DE-588)4139030-1 (DE-588)4148259-1 (DE-588)4121208-3 (DE-588)4129594-8 (DE-588)4117388-0 (DE-588)4059549-3 (DE-588)4125229-9 (DE-588)4027242-4 (DE-588)4059360-5 (DE-588)4038243-6 (DE-588)4047610-8 (DE-588)1071861417 |
| title | Proceedings [October 2 - 6, 1994, Sheraton Washington Hotel, Washington, DC, USA ; test: the next 25 years] |
| title_auth | Proceedings [October 2 - 6, 1994, Sheraton Washington Hotel, Washington, DC, USA ; test: the next 25 years] |
| title_exact_search | Proceedings [October 2 - 6, 1994, Sheraton Washington Hotel, Washington, DC, USA ; test: the next 25 years] |
| title_full | Proceedings [October 2 - 6, 1994, Sheraton Washington Hotel, Washington, DC, USA ; test: the next 25 years] International Test Conference 1994 |
| title_fullStr | Proceedings [October 2 - 6, 1994, Sheraton Washington Hotel, Washington, DC, USA ; test: the next 25 years] International Test Conference 1994 |
| title_full_unstemmed | Proceedings [October 2 - 6, 1994, Sheraton Washington Hotel, Washington, DC, USA ; test: the next 25 years] International Test Conference 1994 |
| title_short | Proceedings |
| title_sort | proceedings october 2 6 1994 sheraton washington hotel washington dc usa test the next 25 years |
| title_sub | [October 2 - 6, 1994, Sheraton Washington Hotel, Washington, DC, USA ; test: the next 25 years] |
| topic | Mikroelektronik (DE-588)4039207-7 gnd Bildverstehen (DE-588)4202022-0 gnd Testen (DE-588)4367264-4 gnd Elektronik (DE-588)4014346-6 gnd Computerunterstütztes Verfahren (DE-588)4139030-1 gnd Computersimulation (DE-588)4148259-1 gnd Entwurf (DE-588)4121208-3 gnd Maschinelles Sehen (DE-588)4129594-8 gnd VLSI (DE-588)4117388-0 gnd Test (DE-588)4059549-3 gnd Datenverarbeitungssystem (DE-588)4125229-9 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Telekommunikation (DE-588)4059360-5 gnd Medizin (DE-588)4038243-6 gnd Prüftechnik (DE-588)4047610-8 gnd |
| topic_facet | Mikroelektronik Bildverstehen Testen Elektronik Computerunterstütztes Verfahren Computersimulation Entwurf Maschinelles Sehen VLSI Test Datenverarbeitungssystem Integrierte Schaltung Telekommunikation Medizin Prüftechnik Konferenzschrift 1994 Washington DC |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006577094&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT internationaltestconferencewashingtondc proceedingsoctober261994sheratonwashingtonhotelwashingtondcusatestthenext25years |