Fifth Eurochip Workshop on VLSI Design Training: 17, 18, 19 October 1994, Dresden, Germany
Gespeichert in:
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| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Grenoble
EUROCHIP
1994
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XI, 465 S. graph. Darst. |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV009928450 | ||
| 003 | DE-604 | ||
| 005 | 19951108 | ||
| 007 | t | ||
| 008 | 941130s1994 d||| |||| 10||| eng d | ||
| 035 | |a (OCoLC)258480723 | ||
| 035 | |a (DE-599)BVBBV009928450 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-29T |a DE-91 | ||
| 084 | |a ELT 272f |2 stub | ||
| 111 | 2 | |a Workshop on VLSI Design Training |n 5 |d 1994 |c Dresden |j Verfasser |0 (DE-588)1900737-1 |4 aut | |
| 245 | 1 | 0 | |a Fifth Eurochip Workshop on VLSI Design Training |b 17, 18, 19 October 1994, Dresden, Germany |c EUROCHIP, service organisation of the CEC VLSI design action |
| 264 | 1 | |a Grenoble |b EUROCHIP |c 1994 | |
| 300 | |a XI, 465 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CAD |0 (DE-588)4069794-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Software |0 (DE-588)4055382-6 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 1994 |z Dresden |2 gnd-content | |
| 689 | 0 | 0 | |a Software |0 (DE-588)4055382-6 |D s |
| 689 | 0 | 1 | |a CAD |0 (DE-588)4069794-0 |D s |
| 689 | 0 | 2 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 1 | 1 | |a Entwurf |0 (DE-588)4121208-3 |D s |
| 689 | 1 | |5 DE-604 | |
| 856 | 4 | 2 | |m GBV Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006576645&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-006576645 | ||
Datensatz im Suchindex
| _version_ | 1804124293591728128 |
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| adam_text | EUROC ILL V 1 2 7 12 17 18 19 25 31 32 38 44 49 50 51 57 63 TABLE OF
CONTENTS FOREWORD ORGANISATION AND AIM VLSI DESIGN: FROM TEACHING TO
RESEARCH CHAIRPERSON : W SCHWARZ, TECHNISCHE UNIVERSITAT DRESDEN TOWARDS
TEACHING SYSTEM DESIGN CONCEPTS: ADVANTAGES AND EXPERIENCES J BORMANS, J
CORNELLS, ETRO/IR1S, VUB, BRUSSELS F VAN DER SCHUEREN, IHAM, ANTWERPEN
IBOLSENS.VSDM/LMEC.LEUVEN THE SEMICUSTOM DESIGN AND TEST PATH, USED FOR
CHIP DESIGN EDUCATION AT DELFT UNIVERSITY R NOUTA, E HENDRIKS,
TECHNISCHE UNIVERSITEIT DELFT 5.8GB/S 16:1 MULTIPLEXER AND 1:16
DEMULTIPLEXER USING 1.2P BICMOS J MIDTGAARD, C SVENSSON, DTU, LYNGBY
TEACHING ANALOG AND HYBRID DESIGN CHAIRPERSON : M DECLERCQ, ECOLE
POLYTECHNIQUE FEDERALE DE LAUSANNE A MIXED INTEGRATED CIRCUIT DESIGN
PRACTICAL PROJECT JF NAVINER, P LOUMEAU, H PETIT, J PORTE, TELECOM,
PARIS TRAINING IN ANALOG/DIGITAL CMOS DESIGN P NORD, BA MOLIN, LUND
UNIVERSITY TEACHING MIXED-MODE INTEGRATED CIRCUIT DESIGN USING A
CUSTOMIZED ANALOG/DIGITAL TRANSISTOR ARRAY UNDER CADENCE ANALOG ARTIST H
ACKER, S SCHWEHR, J VOLLRATH, TECHNISCHE UNIVERSITAT DARMSTADT
FUNDAMENTALS CHAIRPERSON : R UBAR, TALUNNA TECHNIKAULIKOOL EARLY
EXPOSURE TO REAL DESIGN AND IMPLEMENTATION IN A COMPUTER ENGINEERING
COURSE J GARSIDE, M CLARKE, UNIVERSITY OF MANCHESTER COMPLEXITY MEASURES
FOR VER1LOG-HDL MODELS M SCHAFERS, P BLINZER, J REITNER, TECHNISCHE
UNIVERSITAT BRAUNSCHWEIG ANALYZING LARGE STATEMATE MODELS E COCHLOVIUS,
U GOLZE, TECHNISCHE UNIVERSITAT BRAUNSCHWEIG I CURRICULA CHAIRPERSON : M
RENCZ, BUDAPEST! MOSZAKI EGYETEM VLSI DESIGN TRAINING AT THE TECHNICAL
UNIVERSITY OF DRESDEN R SCHUFFNY, W REINHOLD, TECHNISCHE UNIVERSITAT
DRESDEN EDUCATION IN THE AREA OF HIGH-LEVEL DESIGN TECHNIQUES AT TU
DARMSTADT U BAAKE, M GOEDECKE, SA HUSS, M SCHAFFNER, TECHNISCHE
UNIVERSITAT DARMSTADT TEACHING HIGH-SPEED GAASIC-DESIGN P DANIELSEN,
DTU, LYNGBY MICROELECTRONICS AND VLSI DESIGN IN NEW CURRICULA AT THE
FACULTY OF ELECTRONICS WUT A PLITZNER, W KUZMICZ, POLITECHNIKA
WARSZAWSKA VII 69 70 79 85 91 97 99 100 103 109 115 116 120 128 133 139
145 146 152 158 164 170 TEACHING DIGITAL DESIGN CHAIRPERSON : B HOCHET,
ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE AN APPROACH TO VHDL MODELING OF
PROCESSORS: APPLICATION TO INTEL 8051 C PREMONT, N ABOUCHI, R GRISEL,
ICPI, LYON MULTILAB PROJECT A AMARA, M CIAZYNSKI, F AMIEL, JF LEPERE,
1SEP, PARIS EXERCISES ON HIGH LEVEL DESIGN AUTOMATION P THOLE, W
ROSENSTIEL, UNIVERSITAT TUBINGEN PRACTICAL AND EDUCATIONAL ASPECTS OF
ON-UNE ARITHMETIC J ANDERSEN, FT MOLLER, 0 OLSEN, AALBORG UNIVERSITY
SESSION EUROCHIP CHAIRPERSON : A KAESSER, GMD/EUROCHIP ANALOG CIRCUIT
DESIGN + MODELING CHAIRPERSON : A KAISER, INSTITUT SUPERIEUR
D ELECTRONIQUE DU NORD, LILLE A HIGH SPEED, LOW POWER 8-BIT CMOS A/D
CONVERTER DJ FOLEY, JG RYAN, NATIONAL MICROELECTRONICS RESEARCH CENTRE,
CORK A VLSI DESIGN PROJECT FOR CROSSTALK MEASUREMENT E SICARD, A LIAUD,
JY FOUMIOLS, JL NOULLET, 1NSA, TOULOUSE A MONOLITHIC SAMPLE & HOLD
CIRCUIT FOR HIGH-SPEED DIGITAL WAVEFORM ACQUISITION GF AVITABILE, A
CIDRONALI, GF MANES, UNIVERSITA DI FIRENZE VLSI PROCESSOR DESIGN
CHAIRPERSON : A FERRARI, UNIVERSIDADE DE AVEIRO DESIGN OF A RISC/VUW
PROCESSOR D HOUZET, IRTT-ENSEEIHT, TOULOUSE A TUTORIAL FOR ADVANCED VLSI
COURSE: DESIGNING THE 32 BIT DLX MICROPROCESSOR WITH THE ALLIANCE CAD
SYSTEM P BAZARGAN-SABET, J DUNOYER, A GREINER, MM ROSSET-LOUERAT,
UNIVERSITE PIERRE ET MARIE CURIE, PARIS HIGH LEVEL DESIGN OF A RISC
MICROCONTROLLER B WEBER, R REITHER, J FROMWALD, P MANDL, G GRIDLING, D
LOY, TECHNISCHE UNIVERSITAET WIEN A MICROPROCESSOR IN 4 MONTHS:
DEVELOPMENT OF THE FHOP - MICROPROCESSOR - KERNEL VIA VHDL AND LOGIC *
SYNTHESIS T GIERINGER, F ZIMPFER, D JANSEN, FACHHOCHSCHULE OFFENBURG
VHDL-BASED ARCHITECTURAL DESIGN OF GRECO, A HIGH-PERFORMANCE SCREENING
COPROCESSOR D BUYSE, P CNUDDE, R LASURE, J VAN CAMPENHOUT, INDUSTRIE
HOGESCHOOL BME, GENT TEST AND TESTABILITY CHAIRPERSON : E VALDERRAMA,
UNIVERSIDAD AUTONOMA DE BARCELONA FAULT SIMULATION OF VERILOG MODELS
ABOVE THE GATE LEVEL T ROSENTHAL, KP WACHSMANN, TECHNISCHE UNIVERSITAT
BRAUNSCHWEIG A PC-BASED CAD SYSTEM FOR TRAINING DIGITAL TEST R UBAR, A
BULDAS, P PAOMETS, J RAIK, V TULIT.TALLINNA TECHNIKAULIKOOL, TALLINNA
BOUNDARY SCAN CELLS FROM DESIGN TO TEST IN ASIC A DANDACHE, A NASSIH, B
LEPLEY, JP CHARLES, UCM/CLOES, METZ AN EXAMPLE OF BOUNDARY-SCAN
IMPLEMENTATION FOR TEACHING BOARD LEVEL TESTING O FLORENT, E REJOUAN, A
DERIEUX, M HIRECH, UNIVERSITE PIERRE ET MARIE CURIE, PARIS DEFECT
DETECTION BY THE BULK CURRENT G KEMNITZ, H KOHLER, RG SPALLEK,
TECHNISCHE UNIVERSITAT DRESDEN VIII 177 DESIGN METHODOLOGIES AND TOOLS *
CHAIRPERSON : 0 MANCK, TECHNISCHE UNIVERSITAT BERLIN 178 DESIGN OF A
TRANSMISSION FAILURE INDICATOR CHIP IN A UNIVERSITY STUDENT COURSE USING
VHDL J FRICKEL, C KUNTZSCH, U HEINKEL, M SELZ UNIVERSITAT
ERLANGEN-NUMBERG 182 TEACHING EXPERIENCES USING REPROGRAMMABLE GATE
ARRAYS M COLLEY, J STANDEVEN UNIVERSITY OF ESSEX 188 A ROBUST DESIGN
ENVIRONMENT FOR VLSI TRAINING WITH A VERY SHORT LEARNING CURVE P
GROENEVELD, TECHNISCHE UNIVERSITEIT DELFT 194 TEACHING SYSTEM
INTEGRATION USING FPGAS A KLINDWORTH, K LAGEMANN, L LARSSON, B SCHUTZ,
UNIVERSITY OF HAMBURG 200 CHDL++: UNDERSTANDING VHDL IMPLEMENTATION
CONCEPTS BY USING C++ KC POSCH, TECHNISCHE UNIVERSITAET GRAZ 207 SPECIAL
SESSION: FUTURE DEVELOPMENTS IN STRATEGIC AREAS IN MICROELECTRONICS ;
CHAIRPERSON : W SCHWARZ, TECHNISCHE UNIVERSITAT DRESDEN 208 FUTURE
DEVELOPMENTS IN SENSORS AND ACTUATORS W. SANSEN, KU LEUVEN 218 FUTURE
DEVELOPMENTS IN THE TELECOMMUNICATION WORLD J. DANNEELS, ALCATEL BELL
TELEPHONE, ANTWERPEN 225 TECHNOLOGY TRANSFER CHAIRPERSON: A SAUER, 226
IMPLEMENTATION OF A MULTI-FUNCTION SIGNAL DETECTION BLOCK FOR A HELD
PROGRAMMABLE ANALOGUE ARRAY USING MIETEC 2.4)1 CMOS PROCESS AND MENTOR
GRAPHICS SOFTWARE VERSION 8.2 S CHANG, BR HAYES-GILL, C PAULL,
UNIVERSITY OF NOTTINGHAM 232 TRANSFERRING MICROELECTRONIC DESIGN AND
TEST SKILLS TO SME THROUGH END-OF-COURSE PROJECTS S BRACHO, F AZCONDO, M
MARTINEZ, UNIVERSIDAD DE CANTABRIA 238 MICROSWISS CENTER: A NEW WAY FOR
TECHNICAL ENGINEERING SCHOOLS TO COLLABORATE WITH INDUSTRIES JD
CHATELAIN, CENTRE MICROSWISS DE SUISSE OCCIDENTALE F CORTHAY, M JACOMET,
F RAHALI, ECOLE D LNGENIEURS DU VALAIS 243 MICROELECTRONICS IN EUROPE
MODERATOR : G DE JONQUIERES, FINANCIAL TIMES PANELISTS DR METAKIDES,
DIRECTOR RTD: INFORMATION TECHNOLOGIES, DIRECTORATE GENERAL INDUSTRY, EC
DR KNORR, MEMBER OF SIEMENS EXECUTIVE BOARD DR SCHOMMER, MINISTER OF
ECONOMY OF SAXONIA DR CORNU, VICE-PRESIDENT OF ALCATEL 245 STUDENT
DESIGN EXPERIMENTS CHAIRPERSON : F MALOBERTI, UNIVERSITA DI PAVIA 246
THE DESIGN OF AN ASIC FOR DRIVING A SWITCHED RELUCTANCE MOTOR G
CATHEBRAS, LJRMM, MONTPELLIER J CLARE, UNIVERSITY PARK, NOTTINGHAM 252
THE URISC EXERCISE M SCHAFERS, KP WACHSMANN, G TELKAMP, TECHNISCHE
UNIVERSITAT BRAUNSCHWEIG 258 EXPERIENCE ON THE DEVELOPMENT OF A
NEUROEMULATOR SYSTEM N AVELLANA, J CARRABINA, L RABANEDA, E VALDERRAMA,
UNIVERSIDAD AUTONOMA DE BARCELONA 264 STUDENT DESIGN
EXPERIMENTS-REVISITED FJ AAS, I SUNDSBE, THE NORWEGIAN INSTITUTE OF
TECHNOLOGY, TRONDHEIM K 271 HIGH-SPEED DIGITAL DESIGN CHAIRPERSON : A
DER1EUX, UNIVERSITE PIERRE ET MARIE CURIE, PARIS 272 REGISTER-FILE
GENERATOR IN GALLIUM ARSENIDE P ROYANNEZ, A AMARA, ISEP, PARIS M
GLESNER, T HOLLSTEIN, G HOFFMANN, TECHNISCHE UNIVERSITAT DARMSTADT 278
DESIGN OF A HIGH-SPEED DSP CELL LIBRARY C HEGARTY, R JENSEN, S UDHOLM,
NATIONAL MICROELECTRONICS RESEARCH CENTRE, CORK 284 IMPLEMENTATION OF A
BINARY-TO-RNSCONVERTER D BIRRECK, A DROLSHAGEN, W ANHEIER, R LAUR,
UNIVERSITAT BREMEN 290 DESIGN AND EXPLOITATION OF A 26,000 GATE MESSAGE
ROUTING DEVICE BC O NEILL, GC COULSON, JW ELLIS, S CLARK, NOTTINGHAM
TRENT UNIVERSITY 303 ANALOG CIRCUIT DESIGN TRAINING CHAIRPERSON : V
PORRA, TEKNILUNEN KORKEAKOULU, HELSINKI 304 A BICMOS CURRENT CARRIER
TRANSCEIVER ON LOW VOLTAGE POWER LINES M SARTORI, POLITECNICO DI TORINO
MT LAZARESCU, D LOAN, UNIVERSITY POLITEHNICA BUCURESTI 310 TEACHING
FULLCUSTOM DESIGN OF ANALOG BUILDING BLOCKS WTTH EUROCH1P FACILITIES V
LIBERALI, F MALOBERTI, UNIVERSITA DI PAVIA 316 DESIGNS OF MMIC MICROWAVE
AMPLIFIERS BY ENGINEERING STUDENTS AT INPG F NDAGIJIMANA, B CABON,
ENSERG/INPG, GRENOBLE 323 POSTERS 324 SYNTHESIS OF A XILING FPGA VECTOR
PROCESSOR USING VHDL AND POWERVIEW D TAYLOR, THE UNIVERSITY OF
HUDDERSFIELD 330 A MICROPROCESSOR UNDERGRADUATE DESIGN PROJECT R
BEECHINOR, B COUNIHAN, S UDHOLM, NATIONAL MICROELECTRONICS RESEARCH
CENTRE, CORK 336 MULTI-STAGE SIGMA DELTA ANALOGUE TO DIGITAL CONVERTERS
A KEADY, P JOYCE, C LYDEN, J RYAN, NATIONAL MICROELECTRONICS RESEARCH
CENTRE, CORK 342 A VHDL TUTORIAL FOR PERSONAL COMPUTERS J LOPEZ, JC
LOPEZ, ETSI TEIECOMUNICACION, MADRID 346 TEACHING VLSI DESIGN TO
ELECTRONIC ENGINEERS AT UNIVERSIDADE DE AVEIRO AB FERRARI, VC ALVES, DM
SANTOS, UNIVERSIDADE DE AVEIRO 347 AN OPTIMUM SCHEDULE FOR VERY LONG
INTEGER OPERATIONS WITH ADDRESSLESS REGISTER SETS A GROGGER, R POSCH,
TECHNISCHE UNIVERSITAET GRAZ 353 LEARNING PIPELINED ARRAYS TRADE-OFFS
USING STANDARD CELLS E BOEMO, J JAUREGUI, C SANTOS, F MORENO, J
MENESES, ETSI TEIECOMUNICACION, MADRID 359 A REAL TIME SYSTEM FOR
ISOLATED SPEECH RECOGNITION BASED ON VTTERBI ALGORITHM JM FERNANDEZ, P
ALTARES, R PERALTA, F MORENO, J MENESES, ETSI TELECOMUNICACIONES, MADRID
364 ANALOG CELLULAR NEURAL NETWORK DESIGN AS A STUDENT TEAM WORK PROJECT
K HALONEN, A PAASIO, V PORRA, TEKNILLINEN KORKEAKOULU, HELSINKI 369 FAST
PROTOTYPING AND EMULATION OF ASICS USING FPGAS P KINDSMULLER, W PUFFER,
TECHNISCHE UNIVERSITAT MUNCHEN 375 DEVELOPMENT OF A PROGRAMMABLE DIGITAL
CONTROLLER FOR THE IMPLEMENTATION OF A VIRTUAL LAB G DONZELLINI, D
PONTA, S ROSSI, L SCIUTTO, M TAINI, M VALLE, UNIVERSITA DI GENOVA 381
DIGITAL HEART-RATE MONITOR A BOILSON, MJ BURKE, TRINITY COLLEGE DUBLIN
386 HIGH LEVEL MODELING AND SYNTHESIS OF A SIMPLE MICROPROCESSOR WITH
TEST STRUCTURES W DAEMS, M TEMMERMAN, KATHOLIEKE INDUSTRIE^ HOGESCHOOL
ANTWERPEN 392 DECIMATION FILTER FOR SIGMA-DELTA A/D-CONVERTER S BECKER,
W REINHOLD, TECHNISCHE UNIVERSITAT DRESDEN 393 394 400 406 412 416 422
428 429 434 TEACHING COUPLED LAYOUT, PROCESS AND DEVICE DESIGN OF MODERN
SEMICONDUCTOR STRUCTURES R DITTMANN, T GRAETZ, W KLIX, JU SCHLUEFILER,
RG SPALLEK, TECHNISCHE UNIVERSITAT DRESDEN VLSI DESIGN IN A THREE YEAR
ENGINEERING CURRICULUM JL NAVARRO, MC LACRUZ, C SANZ, UNIVERSIDAD
POLITECNICA DE MADRID H CHAOUI, GN LU, S RIGO, CEMIP/UNIVERSITE PARIS 6
ET 7 EXPERIENCE ACCUMULATED BY THE SIMULATION OF AN APPLICATION SPECIFIC
ANALOG INTEGRATED CIRCUIT GPK ECONOMOU, GC ANAGNOSTOPOULOS, CE GOUTIS,
UNIVERSITY OF PATRAS IJSER-FRIENDLYFPMDEOTWNHANIMPROVTDCM^ A KOCH,
TECHNISCHE UNIVERSITAT BRAUNSCHWEIG CONCEPTION OF MICROWAVE MONOLITHIC
INTEGRATED MIXERS BASED ON GAAS FET SWITCHES DEVICES E GOSSE, EA
ALLAMANDO, UNIVERSITE DE LILLE A NEW VHDL-BASED APPROACH IN MULTILEVEL
SIMULATION OF SIGNAL PROCESSING SYSTEMS H GARBE, HI JENTSCHEL, R
KAMINSKI, TECHNISCHE UNIVERSITAT DRESDEN VLSI DESIGN OF AN ADAPTIVE
LATTICE FILTER FOR MULTICHANNEL SIGNAL PROCESSING GO GLENTIS, MM SAMSOM,
GH SLUMP, UNIVERSITEIT TWENTE, ENSCHEDE IMPACT OF A TEMPUS JEP ON
DIGITAL SYSTEMS DESIGN COURSES AT TECHNICAL UNIVERSITY IN ZELONA GORA J
MIRKOWSKI, M ADAMSKI, J SZAJNA, POLITECHNIKA ZIELONA GORA A
CONHGLIMLEMASSIVEY PARALLEL NEUROEMULATOR SYSTEM M ALONSO, 0 BERNAT, R
CAPILLAS, A CARRERAS, J CASTILLO, E CORDOBA, N CRUZ, JA DOBLADO, A
FERNANDEZ, P GARCIA, R HOLGADO, 0 MASCORT, A MARTINEZ, MA MORUNO, M
PEREZ, J PLANA, I ROMERO, J VIVEROS, N AVELLANA, UNIVERSIDAD AUTONOMA DE
BARCELONA 435 CAD TOOL DEMONSTRATIONS 447 EXHIBITION OF COURSE MATERIAL
459 CIRCUITS EXHIBITION 463 INDEX XI
|
| any_adam_object | 1 |
| author_corporate | Workshop on VLSI Design Training Dresden |
| author_corporate_role | aut |
| author_facet | Workshop on VLSI Design Training Dresden |
| author_sort | Workshop on VLSI Design Training Dresden |
| building | Verbundindex |
| bvnumber | BV009928450 |
| classification_tum | ELT 272f |
| ctrlnum | (OCoLC)258480723 (DE-599)BVBBV009928450 |
| discipline | Elektrotechnik |
| format | Conference Proceeding Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01671nam a2200409 c 4500</leader><controlfield tag="001">BV009928450</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">19951108 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">941130s1994 d||| |||| 10||| eng d</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)258480723</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV009928450</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-29T</subfield><subfield code="a">DE-91</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 272f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="111" ind1="2" ind2=" "><subfield code="a">Workshop on VLSI Design Training</subfield><subfield code="n">5</subfield><subfield code="d">1994</subfield><subfield code="c">Dresden</subfield><subfield code="j">Verfasser</subfield><subfield code="0">(DE-588)1900737-1</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Fifth Eurochip Workshop on VLSI Design Training</subfield><subfield code="b">17, 18, 19 October 1994, Dresden, Germany</subfield><subfield code="c">EUROCHIP, service organisation of the CEC VLSI design action</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Grenoble</subfield><subfield code="b">EUROCHIP</subfield><subfield code="c">1994</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XI, 465 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Software</subfield><subfield code="0">(DE-588)4055382-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="y">1994</subfield><subfield code="z">Dresden</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Software</subfield><subfield code="0">(DE-588)4055382-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">GBV Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006576645&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-006576645</subfield></datafield></record></collection> |
| genre | (DE-588)1071861417 Konferenzschrift 1994 Dresden gnd-content |
| genre_facet | Konferenzschrift 1994 Dresden |
| id | DE-604.BV009928450 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T17:43:22Z |
| institution | BVB |
| institution_GND | (DE-588)1900737-1 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006576645 |
| oclc_num | 258480723 |
| open_access_boolean | |
| owner | DE-29T DE-91 DE-BY-TUM |
| owner_facet | DE-29T DE-91 DE-BY-TUM |
| physical | XI, 465 S. graph. Darst. |
| publishDate | 1994 |
| publishDateSearch | 1994 |
| publishDateSort | 1994 |
| publisher | EUROCHIP |
| record_format | marc |
| spelling | Workshop on VLSI Design Training 5 1994 Dresden Verfasser (DE-588)1900737-1 aut Fifth Eurochip Workshop on VLSI Design Training 17, 18, 19 October 1994, Dresden, Germany EUROCHIP, service organisation of the CEC VLSI design action Grenoble EUROCHIP 1994 XI, 465 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier VLSI (DE-588)4117388-0 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf Software (DE-588)4055382-6 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1994 Dresden gnd-content Software (DE-588)4055382-6 s CAD (DE-588)4069794-0 s VLSI (DE-588)4117388-0 s DE-604 Entwurf (DE-588)4121208-3 s GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006576645&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Fifth Eurochip Workshop on VLSI Design Training 17, 18, 19 October 1994, Dresden, Germany VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd Software (DE-588)4055382-6 gnd Entwurf (DE-588)4121208-3 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4069794-0 (DE-588)4055382-6 (DE-588)4121208-3 (DE-588)1071861417 |
| title | Fifth Eurochip Workshop on VLSI Design Training 17, 18, 19 October 1994, Dresden, Germany |
| title_auth | Fifth Eurochip Workshop on VLSI Design Training 17, 18, 19 October 1994, Dresden, Germany |
| title_exact_search | Fifth Eurochip Workshop on VLSI Design Training 17, 18, 19 October 1994, Dresden, Germany |
| title_full | Fifth Eurochip Workshop on VLSI Design Training 17, 18, 19 October 1994, Dresden, Germany EUROCHIP, service organisation of the CEC VLSI design action |
| title_fullStr | Fifth Eurochip Workshop on VLSI Design Training 17, 18, 19 October 1994, Dresden, Germany EUROCHIP, service organisation of the CEC VLSI design action |
| title_full_unstemmed | Fifth Eurochip Workshop on VLSI Design Training 17, 18, 19 October 1994, Dresden, Germany EUROCHIP, service organisation of the CEC VLSI design action |
| title_short | Fifth Eurochip Workshop on VLSI Design Training |
| title_sort | fifth eurochip workshop on vlsi design training 17 18 19 october 1994 dresden germany |
| title_sub | 17, 18, 19 October 1994, Dresden, Germany |
| topic | VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd Software (DE-588)4055382-6 gnd Entwurf (DE-588)4121208-3 gnd |
| topic_facet | VLSI CAD Software Entwurf Konferenzschrift 1994 Dresden |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006576645&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT workshoponvlsidesigntrainingdresden fiftheurochipworkshoponvlsidesigntraining171819october1994dresdengermany |