Proceedings of the seventh International Conference on VLSI Design: January 5 - 8, 1994, Calcutta, India
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Los Alamitos, Calif. u.a.
IEEE Computer Soc. Press
1994
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Nebent.: VLSI design '94. - Design automation of MCM, PCB, and VLSI |
| Beschreibung: | XX, 423 S. Ill., graph. Darst. |
| ISBN: | 0818649909 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV009799618 | ||
| 003 | DE-604 | ||
| 005 | 19960517 | ||
| 007 | t| | ||
| 008 | 940909s1994 xx ad|| |||| 10||| eng d | ||
| 020 | |a 0818649909 |9 0-8186-4990-9 | ||
| 035 | |a (OCoLC)30407610 | ||
| 035 | |a (DE-599)BVBBV009799618 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-739 |a DE-91 |a DE-83 | ||
| 050 | 0 | |a TK7874.75 | |
| 082 | 0 | |a 621.39/5 |2 20 | |
| 084 | |a ZN 4952 |0 (DE-625)157425: |2 rvk | ||
| 084 | |a ELT 272f |2 stub | ||
| 111 | 2 | |a International Conference on VLSI Design |n 7 |d 1994 |c Kalkutta |j Verfasser |0 (DE-588)5128295-1 |4 aut | |
| 245 | 1 | 0 | |a Proceedings of the seventh International Conference on VLSI Design |b January 5 - 8, 1994, Calcutta, India |
| 246 | 1 | 3 | |a VLSI design '94 |
| 264 | 1 | |a Los Alamitos, Calif. u.a. |b IEEE Computer Soc. Press |c 1994 | |
| 300 | |a XX, 423 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Nebent.: VLSI design '94. - Design automation of MCM, PCB, and VLSI | ||
| 650 | 4 | |a Electronic digital computers |x Circuits |v Congresses | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |v Congresses | |
| 650 | 0 | 7 | |a Entwurfsautomation |0 (DE-588)4312536-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 1994 |z Kalkutta |2 gnd-content | |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a Entwurfsautomation |0 (DE-588)4312536-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 856 | 4 | 2 | |m Digitalisierung TU Muenchen |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006483809&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-006483809 | |
Datensatz im Suchindex
| _version_ | 1820882551845158912 |
|---|---|
| adam_text |
Contents
General
Chairs'
Message.xi
Program
Chairs'
Message.xiii
Steering Committee
.xiv
Program Committee
.xv
Conference Committee
.xvi
Reviewers
.xvii
Awards
.xx
Tutorials at VLSI Design
'94.1
Keynote Address
On the Brink of a New Era in VLSI Design
.3
J.B.
Costello
Plenary Session Invited Talk
Gigachip Technology and the Signal Processing Revolution
.4
P.K. Chatterjee
1.
High Level Synthesis I
Chair. A. Kumar, IIT, Delhi, India
1.1
Application of High-Level Synthesis in an Industrial Project
.5
A. Hemani,
B. Karlsson,
M. Fredribson,
К.
Nordqvht,
and B. Fjellborg
1.2
An
Empirical Study on the Effects of Physical Design in High-Level Synthesis
.11
P.K. Jha, C. Ramachandran, N.D. Dutt, andFJ. Kurdahi
1.3
ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis
.17
S. Chaudhuri and R.A. Walker
1.4
FAST: FPGA Targeted
RTL
Structure Synthesis Technique
.21
A.R. Naseer, M.
Balakrìshnan,
and A. Kumar
1.5
Ultra Fine-Grain Template-Driven Synthesis
.25
DJ.
Kolson,
N. Dutt, and
Α.
Nicolau
2.
Parallel Algorithms
Chair. P.
Вапвфе,
UIUC,
Urbana, /Ĺ.,
USA
2.
1 Logic Simulation Using an Asynchronous Parallel Discrete-Event Simulation Model
on a SIMD Machine
.29
S. Seth,
L
Gowen, M. Payne, andD.
Sylwester
2.2
SEMU: A Parallel Processing System for Timing Simulation of Digital
CMOS VLSI Circuits
.33
A. Asthana, M. Laznovsky, andB. Mathews
2.3
CM-SIM: A Parallel Circuit Simulator on a Distributed Memory Multiprocessor
.39
C.V.
Ramamoorthy and
V. Vij
2.4
Parallel Model Evaluation for Circuit Simulation
ой
the PACE Multiprocessor
.45
P. Agrawal, S. Goil, S. Liu, and
JA.
Trotter
2.5
Time- and Cost-Optimal Parallel Algorithms for the Dominance and Visibility Graphs
.49
D. Bhagavathi, S. Olariu, J.L
Schwing,
and
J.
Zhang
3.
Analog Circuit·
Chain
N.B.
Chakraborty,
ІГТ,
Kharagpur,
inaia
3.1
Analog Modeling Using Event-Driven HDL's
.53
D. Dumlugol, D. Webber, andR. Madhavan
3.2
A SPICE Model of RLGC Transmission Line with Error Control
.57
Q. YuandO. Wing
3.3
Multiple Fault Testing in Analog Circuits
.61
N.B.
Hamida and
B. Kaminska
3.4
The Design of Analog Self-Checking Circuits
.67
B. Vinnakota and R. Harjani
3.5
OTA Based Neural Network Architectures with On-Chip Tuning of Synapses
.71
J. Ghosh, P. LaCour, andS. Jackson
4.
Digital Signal Processing
Chêlr: LU.
Patnalk, HSc, Bangalore, India
4.1
TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New
4-» 2
Compressor
.77
D. Ghosh, S.K.
Nandy,
and K. Parthasarathy
4.2
Calculation of Minimum Number of Registers in Arbitrary Life Time Chart
.83
K.K. Parhi
4.3
A VLSI Architecture of an Inverse Discrete Cosine Transform
.87
A.K. Bhattacharya and
S.S.
Haider
4.4
A Fast Algorithm for Performing Vector Quantization and its VLSI Implementation
.91
H. Park and V.K. Prasanna
4.5
A 600MHz Half-Bit Level Pipelined Multiplier Macrocell
.95
D. Ghosh, S.
Sural,
and S.K.
Nandy
5.
DMlgn
for Testability
Chain KJC
Satuja,
U.
of Wisconsin-Madison, Madison, Wl, USA
5.1
A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph
.101
S.-Ł
Tat and D. Bhattacharya
5.2
Simulated Annealing for Target-Oriented Scan
.107
C.P. Ravikumar and H. Rasheed
5.3
A Test Function Architecture for Interconnected Finite State Machines
.113
S. Kanjifol, S.T. Chakradhar, and V.D. Agrawal
5.4
A
Bist
PLA
Design for High Fault Coverage and Testing by an Interleavingly
Crosspoint Counting
.217
MA. Mottalib and P. Dasgupta
5.5
Testability Properties of Local Circuit Transformations with Respect to the Robust
Path-Delay-Fault Model
.123
H.
Hengster,
R.
Drechsler,
and
В.
Becker
β.
Routing
CbalnA-Pml,
UT,
КПлгадриг,
India
6.1
Flipping Modules to Improve Circuit Performance and Routability
. 127
K. Ann and S.
Sahni
6.2
A New Genetic Algorithm for the Channel Routing Problem
. .133
/.
Lienig and K. Thulasiraman
6.3
High Performance Over-the-Cell Routing
. 137
J.E. Crenshaw, S. Tragoudas, andNA. Sherwani
.
VI
6.4
Over-the-Cell Routing Algorithms for Industrial Cell Models
.143
S. Bhingarde, R. Khawaja, A. Panyam, andNA, Sherwani
6.5
Two-Layer Wiring with Pin Preassignments is Easier if the Power Supply Nets
are Already Generated
.149
P. Molitor, U.
Sparmann,
and D. Wagner
7.
High
Uvei
Synthesis II
Chair:
S. Dey,
NEC USA, Princeton, NJ, USA
7.1
Rapid Technology Projection for High-Level Synthesis
.155
P.K.JhaandN.D.Dutt
7.2
Behavioral Design and Prototyping of aFail-Safe System
.159
Y. Min, Y.
Zhou,
Z
Li,
C.
Ye, and Y.Pan
7.3
ВШЕТ:
An Algorithm for Solving the Binding Problem
.163
A. Majumdar, M. Rim, R. Jain, and
R. De
Leone
7.4
A CAD Tool for Design of On-Chip Store
&
Generate Scheme
.169
S. Nandi, B. Vamsi, and P.P. Chaudhuri
7.5
HSIM1 and HSIM2: Object Oriented Algorithms for VHDL Simulation
.175
N.
Ganguly and V. Pitchumani
8.
CMOS Testing
Chair:
S.D.
Shertekar,
SAS, Bangalom,
India
8.1
¡DDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits
.179
S. Chokravarty and S. Suresh
8.2
IDDQ Detection of CMOS Bridging Faults by Stuck-At Fault Tests
.183
S. Hwang, R. Rajsuman, and S. Davidson
8.3
The Effect of Built-in Current Sensors
(BICS)
on Operational and Test Performance
.187
S.M. Menon, Y.K. Malaiya,
Å.P.
Jayasumana, and C.Q.
Tong
8.4
On Testability of Differential Split-Level CMOS Circuits
.191
S.M. Aziz and W.A.J. Waller
8.5
Testable Realizations of CMOS Combinational Circuits for Voltage and Current Testing
.197
K. Biswas andS.
Rai
9.
Layout
Chain B.P. Slnha,
ISI,
Calcutta, India
9.1
On the Synthesis of Gate Matrix Layout
.203
J?. Agarwal and I. Sen Gupta
9.2
An Efficient Hybrid Heuristic for the Gate Matrix Layout Problem in VLSI Design
.207
T. Bagchi and S.K.
Dos
9.3
SAGA: A Unification of the Genetic Algorithm with Simulated Annealing and its Application
to Macro-Cell Placement
.211
H. Esbensen and P. Mazumder
9.4
GLOVE: A Graph-Based Layout Verifier
.215
C.S. Bamji and J. Allen
9.5
A Sea-of-Gates Style FPGA Placement Algorithm
.221
K. Roy, B. Guan, and
С
Sechen
10.
FPGA
Chair:
D.W.
Bouldln, U. of
Твппвѕвв,
Knoxvllle, USA
10.1
A Methodology for Architecture Synthesis of Cascaded
ÏIR
Filters on
TLU
FPGAs
.225
G.N. Rathna, S.K.
Nandy,
and
К.
Parthasarathy
vii
10.2
ffigh Speed Digital Filtering on SRAM-Based FPGAs
.229
A. Giri,
V. Visvanathan, S.K.
Nandy,
and S.K. Ghoshal
10.3
impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled
FPGA Architectures
.
233
M.
Mettendole
10.4
Detailed Routing of Multi-Terminal Nets in FPGAs
.237
A. Chowdhary and D. Bhatia
11.
ASIC and Logic Design
Chain
К.
Pratad,
U. of Massachusetts, Lowell, MA, USA
11.1
A Switch-Memory Chip for Packet Switching at Gigabits per Second
.243
Я.
Kanakia
11.2
A 2KxlK Space Switch ASIC for Use in Digital Exchanges
.247
V.K. Murthy,
K.M.
Kumar, M.B.
Vani,
DJ.
Kumar,
CS.
Mohan, andB.S.
Prosarmi
11.3
Layout Influenced Factorization of Boolean Functions
.251
A. Jaekel, S. Bandyopadhyay, and A. Sengupta
11.4
On Determining Symmetries in Inputs of Logic
Circuite
.255
I. Pomeranz andSM. Reddy
12.
Low Power VLSI
Chêlr:
V.K.
Raj, U.
of Texas
atArílngton,
Arlington,
TX, USA
12.1
Energy Efficient Programmable Computation
.261
A.P.
Chandrakasan, M.B.
Srivastava, andR.W. Brodersen
12.2
Synthesis of Low Power Linear DSP Circuits Using Activity Metrics
.265
A. Chatterjee and R.K. Roy
12.3
Power Constraint Scheduling of Tests
.271
R.M.
Chou, K.K.
Saluja, and V.D. Agrawal
13.
Algorithms/Architectures
Chair: B.
Courtole,
MAG
/ЋШ,
France
13.1
Design of an Application Specific VLSI Chip for Image Rotation
.275
I. Ghosh and B. Majumdar
13.2
Cellular Automata Based VLSI Architecture for Computing Multiplication and Inverses
inGF(2m)
.279
P.P. Choudhury and R. Barm
13.3
Architecture for VLSI Design of CA Based Byte Error Correcting Code Decoders
.283
D.R. Chowdhury and P.P. Chaudhuri
13.4
VLSI Architecture for HDTV Motion Estimation Based on Block-Matching Algorithm
.287
F.-M. Yang, S.
Wolter,
and JR.
Laur
13.5
ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation
.291
M. Kovac andN. Ranganathan
14.
Chain D.K. Bamrfl, I/, of Gueiph, Goe/p/i, Canada
14.
1 An Optimal Design for Parallel Test Generation Based on Circuit Partitioning.
297
D.XimgandD.-Z Wei
.
14.2
D«a Path Testability Evaluation via Functional Testability Measures
.301
M. Jamoussi and
B. Kaminska
14.3
An Improved Deductive Fault Simulator.
. 307
P.R. Sureshkumar, J. Jacob, MX Srinims,
midV.D.AgraZaì
.
viü
14.4
On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition.
311
S.A.
Das, W.-B.
Jone,
A.R. Nayak, and I. Choi
14.5
Low-Cost Redundancy Identification for Combinational Circuits
.315
M.A. Iyer and M. Abramovici
15.
VLSI Technology
Chair: K. Raghunathan, Motorola, Austin,
TX,
USA
15.1
Finite Element Analysis of SIGenpnHBT
.319
G.H.R. Krishna,
N.B.
Chakrabarti, and S. Banerjee
15.2
nOHM
—
A Multi-Process Device Synthesis Tool for Lateral DMOS Structures
.323
S. Natarajan, D. Sahu, and S. Dasgupta
15.3 3D
Effects in VLSI/ULSI MOSFETs: A Novel Analytical Approach to Model
Threshold Voltage
.328
S.K. Lahiri, M.K. Das, A. Das Gupta, and I. Manna
15.4
Parameterized Modeling of Open-Circuit Critical Volume for Three-Dimensional Defects
in VLSI Processing
.333
M.K. Kidambi, A. Tyagi, M.R.
Modani, andM.A.
Bayoumi
15.5
LATCHSIM
—
A Latch-Up Simulator in VLSI CAD Environment for CMOS
and BiCMOS Circuits
.339
A. Bandyopadhyay, P.R. Verma,
A.B.
Bhattacharyya, and M.J. Zarabi
16.
VLSI/WSI Arrays
Chair: A. Agarwal, MIT, Cambridge, MA, USA
16.1
A CORDIC Based Programmable DXT Processor Array
.343
V.K. Anurodha and V. Visvanathan
16.2
Hierarchical Reconfiguration of VLSI/WSI Arrays
.349
D. B hatia, R.
Rajagopalan, and
S.
Katkoorì
16.3
A Linear Systolic Array for
LU
Decomposition
.353
E. Casseau and D. Degrugillier
16.4
An Algorithm to Test Reconfigured RAMs
.359
M. Franklin and K.K. Saluja
16.5
Response Pipelined CAM Chips: The First Generation and Beyond
.365
K. Ghose and V.A. Dharmaraj
17.
FSM Synthesis
Chair: K. Roy, Purdue U., W. Lafayette,
IĄ
USA
17.1
An Integrated Approach to State Assignment and Sequential Element Selection
for FSM Synthesis
.369
M. Mehendale and B.
Mitra
17.2
A New Approach to Synthesis of PLA-Based FSM'
s
.373
CR.
Mohan and P.P. Chakrabarti
17.3
Bitwise Encoding of Finite State Machines
.379
/.
Monteiro,
J.
Kukula,
S. Devadas, and H.
Neto
17.4
Synthesis of
Initializable
Asynchronous
Circuits
.383
S.
Г.
Chakradhar,
S. Banerjee,
R.
К.
Roy, andD.K. Pradhan
17.5
Mechanical
Identification
of Inductive Properties During Verification of
Finite State
Machins
.389
/.
Chakrabarti and D.
Särkar
18.
Design Space Exploration
Chain M. Balakriahnan, IIT, Delhi,
Inaia
18.1
Multìobjectìve
Search in VLSI Design
.395
P. Dasgupta, P.
Mitra,
P.P. Chakrabarti, andS.C. DeSarkar
18.2
Graphical Methodology Language for CAD Frameworks
.401
J. Sfcnicki, M.L
Bushneil,
and
S. Parikh
18.3
An Object Oriented Environment for Modeling and Synthesis of Hardware Circuits
.407
S.
Sarkar
and A. Basu
18.4
Early Exploration of the Multi-Dimensional VLSI Design Space
.413
M.B.
Takla,
D.W.
Bouldìn,
and
D.B. Koch
18.5
Verification of Circuits Described in VHDL through Extraction of Design Intent
.417
Y.V. Hoskote, J. Moondanos,
JA. Abraham,
and
D.S.
Fussell
Author Index
.421 |
| any_adam_object | 1 |
| author_corporate | International Conference on VLSI Design Kalkutta |
| author_corporate_role | aut |
| author_facet | International Conference on VLSI Design Kalkutta |
| author_sort | International Conference on VLSI Design Kalkutta |
| building | Verbundindex |
| bvnumber | BV009799618 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874.75 |
| callnumber-search | TK7874.75 |
| callnumber-sort | TK 47874.75 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4952 |
| classification_tum | ELT 272f |
| ctrlnum | (OCoLC)30407610 (DE-599)BVBBV009799618 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000 c 4500</leader><controlfield tag="001">BV009799618</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">19960517</controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">940909s1994 xx ad|| |||| 10||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0818649909</subfield><subfield code="9">0-8186-4990-9</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)30407610</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV009799618</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-739</subfield><subfield code="a">DE-91</subfield><subfield code="a">DE-83</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7874.75</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield><subfield code="2">20</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4952</subfield><subfield code="0">(DE-625)157425:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 272f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="111" ind1="2" ind2=" "><subfield code="a">International Conference on VLSI Design</subfield><subfield code="n">7</subfield><subfield code="d">1994</subfield><subfield code="c">Kalkutta</subfield><subfield code="j">Verfasser</subfield><subfield code="0">(DE-588)5128295-1</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Proceedings of the seventh International Conference on VLSI Design</subfield><subfield code="b">January 5 - 8, 1994, Calcutta, India</subfield></datafield><datafield tag="246" ind1="1" ind2="3"><subfield code="a">VLSI design '94</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Los Alamitos, Calif. u.a.</subfield><subfield code="b">IEEE Computer Soc. Press</subfield><subfield code="c">1994</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XX, 423 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Nebent.: VLSI design '94. - Design automation of MCM, PCB, and VLSI</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic digital computers</subfield><subfield code="x">Circuits</subfield><subfield code="v">Congresses</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="v">Congresses</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="y">1994</subfield><subfield code="z">Kalkutta</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Digitalisierung TU Muenchen</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006483809&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-006483809</subfield></datafield></record></collection> |
| genre | (DE-588)1071861417 Konferenzschrift 1994 Kalkutta gnd-content |
| genre_facet | Konferenzschrift 1994 Kalkutta |
| id | DE-604.BV009799618 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T17:08:42Z |
| institution | BVB |
| institution_GND | (DE-588)5128295-1 |
| isbn | 0818649909 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006483809 |
| oclc_num | 30407610 |
| open_access_boolean | |
| owner | DE-739 DE-91 DE-BY-TUM DE-83 |
| owner_facet | DE-739 DE-91 DE-BY-TUM DE-83 |
| physical | XX, 423 S. Ill., graph. Darst. |
| publishDate | 1994 |
| publishDateSearch | 1994 |
| publishDateSort | 1994 |
| publisher | IEEE Computer Soc. Press |
| record_format | marc |
| spelling | International Conference on VLSI Design 7 1994 Kalkutta Verfasser (DE-588)5128295-1 aut Proceedings of the seventh International Conference on VLSI Design January 5 - 8, 1994, Calcutta, India VLSI design '94 Los Alamitos, Calif. u.a. IEEE Computer Soc. Press 1994 XX, 423 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Nebent.: VLSI design '94. - Design automation of MCM, PCB, and VLSI Electronic digital computers Circuits Congresses Integrated circuits Very large scale integration Congresses Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1994 Kalkutta gnd-content VLSI (DE-588)4117388-0 s Entwurfsautomation (DE-588)4312536-0 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006483809&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings of the seventh International Conference on VLSI Design January 5 - 8, 1994, Calcutta, India Electronic digital computers Circuits Congresses Integrated circuits Very large scale integration Congresses Entwurfsautomation (DE-588)4312536-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4312536-0 (DE-588)4117388-0 (DE-588)1071861417 |
| title | Proceedings of the seventh International Conference on VLSI Design January 5 - 8, 1994, Calcutta, India |
| title_alt | VLSI design '94 |
| title_auth | Proceedings of the seventh International Conference on VLSI Design January 5 - 8, 1994, Calcutta, India |
| title_exact_search | Proceedings of the seventh International Conference on VLSI Design January 5 - 8, 1994, Calcutta, India |
| title_full | Proceedings of the seventh International Conference on VLSI Design January 5 - 8, 1994, Calcutta, India |
| title_fullStr | Proceedings of the seventh International Conference on VLSI Design January 5 - 8, 1994, Calcutta, India |
| title_full_unstemmed | Proceedings of the seventh International Conference on VLSI Design January 5 - 8, 1994, Calcutta, India |
| title_short | Proceedings of the seventh International Conference on VLSI Design |
| title_sort | proceedings of the seventh international conference on vlsi design january 5 8 1994 calcutta india |
| title_sub | January 5 - 8, 1994, Calcutta, India |
| topic | Electronic digital computers Circuits Congresses Integrated circuits Very large scale integration Congresses Entwurfsautomation (DE-588)4312536-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Electronic digital computers Circuits Congresses Integrated circuits Very large scale integration Congresses Entwurfsautomation VLSI Konferenzschrift 1994 Kalkutta |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006483809&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT internationalconferenceonvlsidesignkalkutta proceedingsoftheseventhinternationalconferenceonvlsidesignjanuary581994calcuttaindia AT internationalconferenceonvlsidesignkalkutta vlsidesign94 |