Proceedings: EDAC, the European Conference on Design Automation ; ETC, European Test Conference ; EUROASIC, the European Event in ASIC Design ; February 28 - March 3, 1994, Paris, France
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Los Alamitos, Calif. u.a.
IEEE Computer Society Press
1994
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXVII, 676 S. graph. Darst. |
| ISBN: | 0818654104 0818654112 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV009661241 | ||
| 003 | DE-604 | ||
| 005 | 20011018 | ||
| 007 | t| | ||
| 008 | 940620s1994 xx d||| |||| 10||| eng d | ||
| 020 | |a 0818654104 |9 0-8186-5410-4 | ||
| 020 | |a 0818654112 |9 0-8186-5411-2 | ||
| 035 | |a (OCoLC)258368432 | ||
| 035 | |a (DE-599)BVBBV009661241 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-29T |a DE-91 |a DE-739 |a DE-83 | ||
| 084 | |a ZN 4940 |0 (DE-625)157423: |2 rvk | ||
| 084 | |a ELT 272f |2 stub | ||
| 111 | 2 | |a European Design and Test Conference |d 1994 |c Paris |j Verfasser |0 (DE-588)5131059-4 |4 aut | |
| 245 | 1 | 0 | |a Proceedings |b EDAC, the European Conference on Design Automation ; ETC, European Test Conference ; EUROASIC, the European Event in ASIC Design ; February 28 - March 3, 1994, Paris, France |c European Design and Test Conference, ED&TC 1994 |
| 264 | 1 | |a Los Alamitos, Calif. u.a. |b IEEE Computer Society Press |c 1994 | |
| 300 | |a XXVII, 676 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Test |0 (DE-588)4059549-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CAD |0 (DE-588)4069794-0 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 1994 |z Paris |2 gnd-content | |
| 689 | 0 | 0 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 0 | 1 | |a CAD |0 (DE-588)4069794-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
| 689 | 1 | 1 | |a Test |0 (DE-588)4059549-3 |D s |
| 689 | 1 | |8 1\p |5 DE-604 | |
| 856 | 4 | 2 | |m Digitalisierung TU Muenchen |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006388288&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-006388288 | |
Datensatz im Suchindex
| _version_ | 1820882550649782272 |
|---|---|
| adam_text |
Contents
Foreword to EDAC-ETC-EuroASIC
'94_xiv
Organizing and Program Committee
_xvi
Technical Program Committee
_xix
Tutorials
_xxii
List of Reviewers
_xxvi
EDAC-ETC-EuroASIC
1995_xxvii
Session 1A: Processor Architecture
Design and Implementation of a High-Performance, Modular, Sorting Engine
_2
G. Alexiou,
Đ.
Stiliadis, and
N.
Kanopoulos
Design of High Complexity Superscalar Microprocessor with the
Portable IDPS ASIC Library
_9
A.
Greiner, L. Lucas, F. Wajsbürt,
and L. Winckel
Taking Advantage of ASICs to Improve Dependability with Very Low Overheads
_14
T. Michel, R. Leveugle, G. Saucier, R. Doucet, and P. Chapier
Session IB: System Level Transformation and Micro Code Generation
Control Flow Optimization for Fast System Simulation and Storage Minimization
_20
F. Franssen, L. Nachtergaele, H, Samsom,
F. Catthoor, and H.
De Man
Maximizing the Throughput of High Performance DSP Applications
Using Behavioral Transformations
_ 25
S.-H. Huang and J.M. Rabaey
Instruction-Set Matching and Selection for DSP and ASIP Code Generation
_31
C.
Liem,
T.
May, and P.
Paulin
Session
1С:
Testing Sequential Circuits
Application of Simple Genetic Algorithms to Sequential Circuit Test Generation
_40
E.M. Rudnick, J.G. Holm, D.G. Saab, and J.H.
Patel
TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits
_46
S.
Gai,
PJL·.
Montessoro, M. Sonza
Reorda
A Functional Approach to Delay Faults Test Generation for Sequential Circuits
_51
F. Fummi, D. Sciuto, and M.
Serra
Session 2A: System Design and Mixed A/D Synthesis
Logic Synthesis and Verification of the CPU and Caches of a Mainframe System
_60
H
Jí.
Nguyen, J.P.
Tua!,
L.
Dueousso,
M.
Thill, and P.
Vallet
ICM2
1С:
A New ATM Switching Element for
2.48
Gb/s Communications
_65
F.
Calvo,
P. Plaza, and P,
Mateos
Advanced Analog Circuit Design on a Digital Sea-of-Gates Array
_70
R. van
Dongen
and V. Rikkink
Switched Current
Sigma-Delta
A/D Converter for a CMOS Subscriber
Line Analog Front End
_75
D. Gevaert, J. Vanneuvffle, J.
Nedved,
and J. Sevenhans
Session 2B: Circuit Optimization and Partitioning
Delay Reduction by Segment Substitution
_82
H. Ahuja and P.R. Menon
Introduction of Permissible Bridges with Application to Logic Optimization after
Technology Mapping
_87
B.
Rohfleisch
and F. Brglez
High-Level Synthesis of Digital Circuits by Finding
Fixpoints_94
L.
Ghatraju, M.H.
Abd-El-Barr, and
С.
McCrosky
FPGA Partitioning for Critical Paths
_99
Đ.
Brašen
and G. Saucier
Session 2C: BIST Techniques
A Low Cost BIST Methodology and Associated Novel Test Pattern Generator
_106
S.-P.
Lin, S.K.
Gupta, and MA.
Breuer
Signature Analysis for Sequential Circuits with Reset
_113
A.P. Stroele
Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST
_119
LG. Harris and A. Orailoglu
A Fragmented Register Architecture and Test Advisor for BIST
_124
R.J.
Літоті
and D.J. Traynor
Session
ЗА:
Finite State Machine Verification
Bug Identification of a Real Chip Design by Symbolic Model Checking
_132
B. Chen, M. Yamazaki, and M. Fujita
A State Space Decomposition Algorithm for Approximate FSM Traversal
_137
H. Cho, G.D. Hachtel, E.
Macii,
M.
Poncino,
F. Somenzi
An OBDD-Representation of
Statecharts_142
J.HelbigandP.Kelb
Panel Session 3B: Libraries, Models, and Modeling: The Real Challenge
Coordinator: J.
Mucha,
University of Hannover, Germany
Chairman: E.
Barke,
University of Hannover, Germany
Panel:
J. Benkoski, SGS-Thomson Microelectronics, France
P. Brieaud, Compass Design Automation, France
S.
Hamacher,
Mentor Graphics, Germany
D. Laurent, BULL
SA,
France
W.
Ries,
Siemens AG-Semiconduetor Group, Germany
W. Stronski, Cadence Design Systems, Germany
P. van Staa, Robert Bosch GmbH, Germany
vi
Session
ЗС:
Fault
Modeling
A Functionality Fault Model: Feasibility and Applications
_152
Á. Zem
va, F.
Brglez,
К.
Kozminski, and
B. Zaje
Modeling of Broken Connections Faults in CMOS ICs
_159
M.
Favelli,
M.
Dalpasso, P.
Olivo,
and B.
Ricco
Generating Test Patterns for Bridge Faults in CMOS ICs
_165
B. Chess and T. Larrabee
A Hierarchical Approach to Fault Collapsing
_171
IL
Hahn,
R.
Krieger, and
В.
Becker
Session 4A: Synchronous Finite State Machines
Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock
Relation and MG-Decomposition Approach
_178
K.-J. Lin, J.-W. Ruo, and C.-S. Lin
State Minimization of
Pseudo
Non-Deterministic FSMs
_184
Y. Watanabe and R.K. Brayton
Nondeterministic Finite-State Machines and Sequential Don't Cares
_192
M. Damiani
Session 4B: New BDD-Concepts
Boolean Manipulation with Free BDDs. First Experiment Results
_200
J. Bern, J. Gergov,
С
Meinel, and
A. Slobodová
An Extended OBDD Representation for Extended FSMs
_208
M.
Langevin
and E. Cerny
Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine
_214
G.D. Hachtel, E.
Macii,
A. Pardo,
and F. Somenzi
Session 4C: Applications of Boundary Scan
Self Testable Boards with Standard IEEE
1149.5
Module Test and Maintenance (MTM)
Bus Interface
_:_220
O.F. Haberl and T.
Kropf
Random Testing of Interconnects in a Boundary Scan Environment
_226
C.Su
Boundary Scan Testing Combined with Power Supply Current Monitoring
_232
M.
Kärkkäinen, K. Tiensyrjä,
and
M.
Weissenf elt
Session 5A:
DSP
Implementations
Implementation of a CORDIC Processor for CFFT Computation in Gallium
Arsenide Technology
_238
R.
Sarmiento
and K. Eshraghian
PLFP256: A Pipeline Fourier Processor
_245
F. Pogodalla and P. Coulomb
A VLSI Implementation of Parallel Fast Fourier Transform
_250
A. Vacher, M.
Benkhebbab, A. Guyot,
T. Rousseau, and
A. Skaf
va
Design
of a Digital Neural Chip: Application to Optical Character Recognition by
Neural Network
_-------------------------------------256
D.
Jacquet
and G. Saucier
Session 5B: Algorithmic Transformations in High-Level Synthesis
An Algorithm for Array Variable Clustering
_262
L. Ramachandran,
D.D.
Gaj
ski, and V. Chaiyakul
Transforming Linear Systems for Joint Latency and Throughput Optimization
_267
M.B. Srivastava and M. Potkonjak
Genesis: A Behavioral Synthesis System for Hierarchical Testability
_272
S. Bhatia and N.K. Jha
A Synthesis Method for Mixed Synchronous/Asynchronous Behavior
_277
T.-Y. Wu, T-C. Tien, A. C.-H. Wu, and Y.-L. Lin
Session 5C: DFT for Delay Faults and Sequential Machines
A New BIST Approach for Delay Fault Testing
_284
A. Vuksic and
К
Fuchs
BIST Test Pattern Generators for Stuck-Open and Delay Testing
_289
C.-A. Chen and S.K. Gupta
Synthesis of Delay-Verifiable Two-Level Circuits
_297
W. Ke and P.R. Menon
Synthesis of Sequential Machines with Reduced Testing Cost
_302
S.-J. Wang
Session 6A: Estimation During High-Level Synthesis
Incorporating the Controller Effects During Register Transfer Level Synthesis
_308
С
Ramachandran and
F
Л.
Kurdahi
An Algorithm for Generation of Behavioral Shape Functions
_314
N.D. Holmes and
D.D.
Gajski
Optimal Operation Scheduling Using Resource Lower Bound Estimations
_319
M.E. Dalkilic and V. Pitchumani
Optimization of Address Generator Hardware
_325
D.M.
Grant, J. van
Meerbergen,
and P.E JL
Lippens
Session 6B: Towards Statistical and High-Level Timing Analysis
Predicting Circuit Performance Using Circuit-Level Statistical Timing Analysis
_332
EJB. Brashear,
N.
Menezes,
С.
Oh, L.T. Pillage, and M.R. Mercer
Towards Incorporating Device Parameter Variations in Timing Analysis
_338
M.
Sivaraman
and
АлГ.
Stroj
was
A New Model to Uniformly Represent the Function and Timing of
MOS
Circuits and its
Application to VHDL Simulation
_343
J.
Frößl
and T.
Kropf
Taking Advantage of High Level Functional Information to Refine Timing Analysis and
Timing Modeling
_349
C. Safinia, R, Leveugle, and G. Saucier
VOI
Session 6C:
Bridging Faults in Testing
Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability
_ 356
R.
Rodríguez-Montañés
and J. Figueras
Transforming Sequential Logic in Digital CMOS ICs for Voltage and Ijjdq Testing
_361
N.
Sachdev
Test of Bridging Faults in Scan-Based Sequential Circuits
_366
E. Isern and J. Figueras
A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT
_371
R. McGrowen and FJT. Ferguson
Session 7A: Specification and Synthesis of System Interfaces
A Generalized Signal Transition Graph Model for Specification of Complex Interfaces
_378
P.
Vanbekbergen,
С.
Ykman-Couvreur,
В.
Lin, and
H. De
Man
Interface
Controller Synthesis from Requirement Specifications
_385
F. Korf
and R.
Sehlör
Synthesis of System-Level Bus Interfaces
_395
S. Narayan and
D.D.
Gajski
Panel Session 7B:
New Design Techniques, How Are They Influenced by Test?
Coordinator: J.
Mucha,
University of Hannover, Germany
Chairman: T.W. Williams, IBM, US
Panel:
K. Baker, Philips, The Netherlands
R. Camposano, Synopsys, US
F. Cathoor,
ШЕС,
Belgium
B.
Courtois, INPG/TIMA,
France
T. Gheewala, Crosscheck, US
Y. Zorian, AT&T, US
Session 7C: Routing
A Genetic Algorithms for the
Steiner
Problem in a Graph
_402
H. Esbensen and P. Mazumder
On Design Rule Correct Maze Routing
_407
E.P. Huijbregts, J.TJ. van Eijndhoven,
and J-A-G. Jess
An Efficient Router for 2-D Field Programmable Gate Arrays
_412
Y.-L. Wh and M. Marek-Sadowska
Session 8A: Performance Issues in Physical Design
A Method for Reducing Power Consumption of CMOS Logic Based on
Signal Transition Probability
_420
J.
Aki
ta
and
К.
Asada
Cell Height Driven Transistor Sizing in a Cell Based Module Design
_425
H.R.
Lin, C.-L. Chou,
Y.-C. Hsu, and T.-T. Hwang
Non-Tree Routing
_430
Б.А.
McCoy and G. Robins
ix
Panel
Session
8В:
Small and Medium Sized Industries (SMIs),
Do They Get What They Need?
Coordinator: J.
Mucha,
University of Hannover, Germany
Chairman: G.A. Schwippert,
СМЕ
Delft, The Netherlands
Panel:
D.
Langlois,
MISIL
Technologies, France
A.T.
Sauer,
SNI,
Germany
O. R0nmng,
Nordic VLSI, Norway
W. Rehr,
IAM,
Germany
R.L. van
der Valk,
Bureau van
der Valk,
The Netherlands
A.D.
Milne, Wolfson Microelectronics Ltd., UK
Session 8C: Various Views on Testing Efficiency
Fault Modeling and Defect Level Projections in Digital ICs
_436
J.T.
Sousa,
Г.М.
Gonçalves, J.P. Teixeira,
and
T.W.
Williams
Probability Analysis for CMOS Floating Gate Faults
_443
H. Xue, C.
Di,
and JJV.G, Jess
M-Testability: An Approach for Data-Path Testability Evaluation
_449
M. Jamoussi and
B. Kaminska
Session 9A: Design Methodologies for the System-Level
A System-Design Methodology: Executable-Specification Refinement
_458
D.D.
Gajski, F. Vahid, and S. Narayan
Interactive System-Level Partitioning with PARTIF
_464
T.B. Ismail, K. O'Brien, and A. Jerraya
A Development Environment for the Cosynthesis of Embedded
Software/Hardware Systems
_469
M. Edwards and J. Forrest
High-Level Design Validation Using Algorithmic Debugging
_474
J. Naganuma, T. Ogura, and T. Hoshino
Session 9B: Applications of Scheduling in High-Level Synthesis
Component Selection, Scheduling, and Control Schemes for High Level Synthesis
_482
B. Rouzeyre,
D. Dupont,
and G. Sagnes
Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with
Delay Line Optimization
_490
F. Depuydt, W. Geurts, G. Goossens, and H.
De Man
Scheduling with Environmental Constraints Based on Automata Representations
_495
JT.C.-Y. Yang, G.
De Micheli,
and
M. Damiani
Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures
_502
K, Schoofs, G. Goossens, and H.
De Man
Session 9C: Delay Test
TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator
_508
MLC. Lin, JM. Chen, and CL. Lee
Efficient
Path
Identification
for Delay Testing
—
Time and Space Optimization
_513
H.
Wittmann
and M. Henftling
Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis
_518
D. Dumas, P.
Girard,
С
Landrault, and S. Pravossoudovitch
Gate-Delay Fault Test with Conventional Scan-Design
_524
A. Kunzmann and
F. Böhland
Session 10A: Tools and Methods for Analogue System Design
A Methodology for Analog Design Automation in Mixed-Signal ASICs
_530
S. Donnay, K. Swings, G. Gielen, W.
Sansen,
W.
Kruiskamp, and D. Leenaerts
A Graphical Approach to Analogue Behavioural Modelling
_535
Y.
Moser,
P. Nussbaum, H.P.
Amana,
L.
Astier,
and
F. Pellandini
An
Overview of Analogue Optimisation Using "AD-OPT"
_540
Б.
Byrne, O. McCarthy,
Đ.
Lucas, and
B. Donnelian
A Reduced-Swing Data Transmission Scheme for Resistive Bus Lines in VLSIs
_546
M. Ikeda and K.
Asada
Session 10B: Logic, Circuit, and Yield Simulation Technologies
Logic and Fault Simulation by Cellular Automata
_552
Y.-L. Li and C.-W. Wu
Variable Accuracy Device Modeling for Event-Driven Circuit Simulation
_557
K.W. Michaels and A.J. Strojwas
An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits
_562
J.-H.
Wang, J.-T.
Fan, and W.-S. Feng
An Efficient Yield Optimization Method Using a Two Step Linear Approximation of
Circuit Performance
_567
Z. Wang and
S.W.
Director
Session IOC: DFT for Datapaths, Controllers, and Arrays
Efficient Implementations of Self-Checking Multiply and Divide Arrays
_574
M. Nicolaidis and H. Bederr
Synthesis of Self-Testable Controllers
_580
S.
Hellebrand
and H.-J.
Wunderlich
A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability
_586
T. Kim, K.-S.
Chang, and
CL.
Liu
Automatic Synthesis of BISTed Data Paths from High Level Specification
_591
MX.
Flottes,
D.
Hämmad,
and
B. Rouzeyre
Session 11A: Framework Services for Productivity Improvement
HANDICAP
—
A System for Design Consulting
_600
M.
Sträube,
W.
Wilkes, and G. Schlageter
Flow Management Requirements of a Test Harness for Testing the Reliability of an
Electronic CAD System
_605
G,
Bartels,
P.
Kist,
К
Schot,
and
M.
Sim
χι
Distributed Computing, Automatic Design, and Error Recovery in the
Ulysses II Framework
_._--------------------------------610
S. Parikh, M.L.
Bushneil,
J.
Sienicki,
and R. Ganesh
Session 11B: Techniques and Applications for BDDs
Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions
_620
S.-C Chang,
D.I.
Cheng, and M. Marek-Sadowska
Timing Analysis of Combinational Circuits using ADDs
_625
R.I. Bahar, H. Cho, G.D. Hachtel, and E.
Macii,
and F. Somenzi
Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization
_630
B. Wurth and
N.
Wehn
Session 11C: High-Level Verification
System-Level Modeling and Verification: A Comprehensive Design Methodology
_636
P.
С
amurati,
F.
Corno,
P.
Prìnetto,
С.
Bayol,
and B.
Soulas
Clean Formal Semantics for VHDL
_ 641
P.T.
Breuer,
L.
Sánchez Fernández, and
С.
Delgado
Шооѕ
Control
Path Oriented Verification of Sequential Generic Circuits with
Control and Data Path
_648
K. Schneider, T.
Kropf,
and R. Kumar
Poster Session
The Russian EDA Standards Activities
_.654
NM-Vitsyn
"Underground Capacitors"
—
Very Efficient Decoupling for High Performance
UHF
Signal Processing ICs
_655
T. Johansson, L.R, Virtanen, and J.M.
Gobbi
Design of a Real Time Geometric Classifier
_656
M. Robert, S. Turgis, P. Gorria, and
J. Mitéran
From Behavioral Description to Systolic Array Based Architectures
_657
A. Balboni, C.
Costi,
F. Fummi,
and
D.
Sciuto
Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS
Combinational Circuits
_658
A. Abderrahman,
B. Kaminska,
and Y.
Savaria
AREAL:
Automated Reasoning Expert for Analog Layout
_659
H.H.
Ahmad and
ИЛ.
Mack
An Optimizable Model for Process Independent Symbolic Design
_660
J.-C. Dufourd and J.-F. Naviner
Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning
_661
W.C. Wu. CX. Lee, and W.Y. Iin
A Suggestion for Accelerating the Analog Fault Simulation
_662
W.
Vermeiren,
В.
Sträube,
and
G.
Eist
Software Implementation
and Statistical Optimization of Some
Electronic Component's Lifetime
_663
K.C. Kouakou
Physical Modeling of linearity Errors for the Diagnosis of High Resolution
R-2R
D/A
Converters
_664
A. Boni, G.
CMorboli,
G.
Franco,
S.
Mazzoleni, and M.
Ostacoli
XU
A Model-Based Approach to Analog Fault Diagnosis Using
Techniques from Optimization
_665
S. Ahmed, P.Y.K. Cheung, and P. Collins
Functional Tests for Ring-Address SRAM-Type FIFOs
_666
A. J. van
de Goor,
I.
Schanstra,
and
Y.
Zorian
Testability of Circuits Derived from Functional Decision Diagrams
_667
B. Becker and R.
Drechsler
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking
_668
O.
Florent,
A. Greiner, M. Hirech, and E. Rejouan
Multilevel Logic Synthesis of Very High Complexity Circuits
_669
L. Burgun,
N.
Dictus, A. Greiner,
E. Pradho, and C. Sarwary
Signal Transition Graph Transformation for Initializability
_670
S. Banerjee, R.K. Boy, S.T. Chakradhar,
and D.K. Pradhan
Synthesis of Application-Specific Multiprocessor Systems
_671
M.K. Dhodhi, I. Ahmad, and CY-R. Chen
Generating Synchronous Timed Descriptions of Digital Receivers from Dynamic
Data Flow System Level Configurations
_672
P. Zepler and
T. Grötker
Index of Authors
_673
ХШ |
| any_adam_object | 1 |
| author_corporate | European Design and Test Conference Paris |
| author_corporate_role | aut |
| author_facet | European Design and Test Conference Paris |
| author_sort | European Design and Test Conference Paris |
| building | Verbundindex |
| bvnumber | BV009661241 |
| classification_rvk | ZN 4940 |
| classification_tum | ELT 272f |
| ctrlnum | (OCoLC)258368432 (DE-599)BVBBV009661241 |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000 c 4500</leader><controlfield tag="001">BV009661241</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20011018</controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">940620s1994 xx d||| |||| 10||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0818654104</subfield><subfield code="9">0-8186-5410-4</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0818654112</subfield><subfield code="9">0-8186-5411-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)258368432</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV009661241</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-29T</subfield><subfield code="a">DE-91</subfield><subfield code="a">DE-739</subfield><subfield code="a">DE-83</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4940</subfield><subfield code="0">(DE-625)157423:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 272f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="111" ind1="2" ind2=" "><subfield code="a">European Design and Test Conference</subfield><subfield code="d">1994</subfield><subfield code="c">Paris</subfield><subfield code="j">Verfasser</subfield><subfield code="0">(DE-588)5131059-4</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Proceedings</subfield><subfield code="b">EDAC, the European Conference on Design Automation ; ETC, European Test Conference ; EUROASIC, the European Event in ASIC Design ; February 28 - March 3, 1994, Paris, France</subfield><subfield code="c">European Design and Test Conference, ED&TC 1994</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Los Alamitos, Calif. u.a.</subfield><subfield code="b">IEEE Computer Society Press</subfield><subfield code="c">1994</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXVII, 676 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Test</subfield><subfield code="0">(DE-588)4059549-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="y">1994</subfield><subfield code="z">Paris</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Test</subfield><subfield code="0">(DE-588)4059549-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Digitalisierung TU Muenchen</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006388288&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-006388288</subfield></datafield></record></collection> |
| genre | (DE-588)1071861417 Konferenzschrift 1994 Paris gnd-content |
| genre_facet | Konferenzschrift 1994 Paris |
| id | DE-604.BV009661241 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T17:08:41Z |
| institution | BVB |
| institution_GND | (DE-588)5131059-4 |
| isbn | 0818654104 0818654112 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006388288 |
| oclc_num | 258368432 |
| open_access_boolean | |
| owner | DE-29T DE-91 DE-BY-TUM DE-739 DE-83 |
| owner_facet | DE-29T DE-91 DE-BY-TUM DE-739 DE-83 |
| physical | XXVII, 676 S. graph. Darst. |
| publishDate | 1994 |
| publishDateSearch | 1994 |
| publishDateSort | 1994 |
| publisher | IEEE Computer Society Press |
| record_format | marc |
| spelling | European Design and Test Conference 1994 Paris Verfasser (DE-588)5131059-4 aut Proceedings EDAC, the European Conference on Design Automation ; ETC, European Test Conference ; EUROASIC, the European Event in ASIC Design ; February 28 - March 3, 1994, Paris, France European Design and Test Conference, ED&TC 1994 Los Alamitos, Calif. u.a. IEEE Computer Society Press 1994 XXVII, 676 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Test (DE-588)4059549-3 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1994 Paris gnd-content Schaltungsentwurf (DE-588)4179389-4 s CAD (DE-588)4069794-0 s DE-604 Integrierte Schaltung (DE-588)4027242-4 s Test (DE-588)4059549-3 s 1\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006388288&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Proceedings EDAC, the European Conference on Design Automation ; ETC, European Test Conference ; EUROASIC, the European Event in ASIC Design ; February 28 - March 3, 1994, Paris, France Schaltungsentwurf (DE-588)4179389-4 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Test (DE-588)4059549-3 gnd CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4027242-4 (DE-588)4059549-3 (DE-588)4069794-0 (DE-588)1071861417 |
| title | Proceedings EDAC, the European Conference on Design Automation ; ETC, European Test Conference ; EUROASIC, the European Event in ASIC Design ; February 28 - March 3, 1994, Paris, France |
| title_auth | Proceedings EDAC, the European Conference on Design Automation ; ETC, European Test Conference ; EUROASIC, the European Event in ASIC Design ; February 28 - March 3, 1994, Paris, France |
| title_exact_search | Proceedings EDAC, the European Conference on Design Automation ; ETC, European Test Conference ; EUROASIC, the European Event in ASIC Design ; February 28 - March 3, 1994, Paris, France |
| title_full | Proceedings EDAC, the European Conference on Design Automation ; ETC, European Test Conference ; EUROASIC, the European Event in ASIC Design ; February 28 - March 3, 1994, Paris, France European Design and Test Conference, ED&TC 1994 |
| title_fullStr | Proceedings EDAC, the European Conference on Design Automation ; ETC, European Test Conference ; EUROASIC, the European Event in ASIC Design ; February 28 - March 3, 1994, Paris, France European Design and Test Conference, ED&TC 1994 |
| title_full_unstemmed | Proceedings EDAC, the European Conference on Design Automation ; ETC, European Test Conference ; EUROASIC, the European Event in ASIC Design ; February 28 - March 3, 1994, Paris, France European Design and Test Conference, ED&TC 1994 |
| title_short | Proceedings |
| title_sort | proceedings edac the european conference on design automation etc european test conference euroasic the european event in asic design february 28 march 3 1994 paris france |
| title_sub | EDAC, the European Conference on Design Automation ; ETC, European Test Conference ; EUROASIC, the European Event in ASIC Design ; February 28 - March 3, 1994, Paris, France |
| topic | Schaltungsentwurf (DE-588)4179389-4 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Test (DE-588)4059549-3 gnd CAD (DE-588)4069794-0 gnd |
| topic_facet | Schaltungsentwurf Integrierte Schaltung Test CAD Konferenzschrift 1994 Paris |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006388288&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT europeandesignandtestconferenceparis proceedingsedactheeuropeanconferenceondesignautomationetceuropeantestconferenceeuroasictheeuropeaneventinasicdesignfebruary28march31994parisfrance |