Circuit synthesis with VHDL:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston u.a.
Kluwer
1994
|
| Schriftenreihe: | The Kluwer international series in engineering and computer science
261 : VLSI, computer architecture and digital signal processing |
| Schlagworte: | |
| Beschreibung: | XVI, 221 S. graph. Darst. |
| ISBN: | 0792394291 |
Internformat
MARC
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| 084 | |a DAT 190f |2 stub | ||
| 100 | 1 | |a Airiau, Roland |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Circuit synthesis with VHDL |c Roland Airiau, Jean-Michel Berge and Vincent Olive |
| 264 | 1 | |a Boston u.a. |b Kluwer |c 1994 | |
| 300 | |a XVI, 221 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a The Kluwer international series in engineering and computer science |v 261 : VLSI, computer architecture and digital signal processing | |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Bergé, Jean-Michel |e Verfasser |4 aut | |
| 700 | 1 | |a Olive, Vincent |e Verfasser |4 aut | |
| 830 | 0 | |a The Kluwer international series in engineering and computer science |v 261 : VLSI, computer architecture and digital signal processing |w (DE-604)BV023545171 |9 261 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-006387311 | ||
Datensatz im Suchindex
| _version_ | 1804124003397271552 |
|---|---|
| any_adam_object | |
| author | Airiau, Roland Bergé, Jean-Michel Olive, Vincent |
| author_facet | Airiau, Roland Bergé, Jean-Michel Olive, Vincent |
| author_role | aut aut aut |
| author_sort | Airiau, Roland |
| author_variant | r a ra j m b jmb v o vo |
| building | Verbundindex |
| bvnumber | BV009660076 |
| classification_rvk | ST 250 |
| classification_tum | DAT 190f |
| ctrlnum | (OCoLC)831626815 (DE-599)BVBBV009660076 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV009660076 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T17:38:45Z |
| institution | BVB |
| isbn | 0792394291 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006387311 |
| oclc_num | 831626815 |
| open_access_boolean | |
| owner | DE-29T DE-91 DE-BY-TUM DE-83 DE-11 DE-188 |
| owner_facet | DE-29T DE-91 DE-BY-TUM DE-83 DE-11 DE-188 |
| physical | XVI, 221 S. graph. Darst. |
| publishDate | 1994 |
| publishDateSearch | 1994 |
| publishDateSort | 1994 |
| publisher | Kluwer |
| record_format | marc |
| series | The Kluwer international series in engineering and computer science |
| series2 | The Kluwer international series in engineering and computer science |
| spelling | Airiau, Roland Verfasser aut Circuit synthesis with VHDL Roland Airiau, Jean-Michel Berge and Vincent Olive Boston u.a. Kluwer 1994 XVI, 221 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier The Kluwer international series in engineering and computer science 261 : VLSI, computer architecture and digital signal processing VHDL (DE-588)4254792-1 gnd rswk-swf VHDL (DE-588)4254792-1 s DE-604 Bergé, Jean-Michel Verfasser aut Olive, Vincent Verfasser aut The Kluwer international series in engineering and computer science 261 : VLSI, computer architecture and digital signal processing (DE-604)BV023545171 261 |
| spellingShingle | Airiau, Roland Bergé, Jean-Michel Olive, Vincent Circuit synthesis with VHDL The Kluwer international series in engineering and computer science VHDL (DE-588)4254792-1 gnd |
| subject_GND | (DE-588)4254792-1 |
| title | Circuit synthesis with VHDL |
| title_auth | Circuit synthesis with VHDL |
| title_exact_search | Circuit synthesis with VHDL |
| title_full | Circuit synthesis with VHDL Roland Airiau, Jean-Michel Berge and Vincent Olive |
| title_fullStr | Circuit synthesis with VHDL Roland Airiau, Jean-Michel Berge and Vincent Olive |
| title_full_unstemmed | Circuit synthesis with VHDL Roland Airiau, Jean-Michel Berge and Vincent Olive |
| title_short | Circuit synthesis with VHDL |
| title_sort | circuit synthesis with vhdl |
| topic | VHDL (DE-588)4254792-1 gnd |
| topic_facet | VHDL |
| volume_link | (DE-604)BV023545171 |
| work_keys_str_mv | AT airiauroland circuitsynthesiswithvhdl AT bergejeanmichel circuitsynthesiswithvhdl AT olivevincent circuitsynthesiswithvhdl |