Digest of technical papers:
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Piscataway, NJ
IEEE Service Center
1992
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | X, 120 S. Ill., graph. Darst. |
| ISBN: | 0780307011 078030702X 0780307038 |
Internformat
MARC
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| 245 | 1 | 0 | |a Digest of technical papers |c Symposium on VLSI Circuits 1992 ; IEEE Solid-State Circuits Council |
| 264 | 1 | |a Piscataway, NJ |b IEEE Service Center |c 1992 | |
| 300 | |a X, 120 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Computers |x Circuits |x Congresses | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Congresses | |
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Datensatz im Suchindex
| _version_ | 1804123925621243904 |
|---|---|
| adam_text | CONTENTS
Foreword
.............................................................................................................................................
Session
1 :
Welcome and Plenary Session I [Grand Ballrooms I
&
II]
1.2
Multimedia Communication
-
Present
&
Future
T. Kamae
.......................................................................................................................;...........
1.3
Next Generation Automotive Electronics: The Impact on Technologies and Design
J. Melbert
...................................................................................................................................
8
Session
2:
Microprocessors [Grand Ballrooms I
&
II]
2.1
A 100-MHz Superscalar PA-RISC CPU/Coprocessor Chip
J. Yetter, B. Miller, W. Jaffe
,
E. DeLano
..................................................................................
10
2.2
80-MHz
MCM
Microprocessor/Cache Subsytem Based on
i486™
Architecture
R. Sundahl, M. Aghazadeh, B. Lieberman, T. Schreyer,
W. Siu, R.
Suarez,
J.Wilson
..................................................................................................................................14
2.3
A 66-MHz Configurable Secondary Cache Controller with Primary
Cache Copyback Support
P. Reed, M. Alexander, B. Beavers, R.
Evers,
S.
Gary,
G. Gerosa,
A. Grossman,
С
Gutierrez, G. Jackson, M. Kearney, R. Lewelling, J. Slaton, R. Stanphill
...........................16
2.4
A Neural Network Embedded Processor With a Dynamically
Reconfigurable
Pipeline Architecture
T. Satonaka, Y. Tamura, T. Morishita, A. Inoue, S. Katsu, T. Otsuki, G.
Kano
........................18
Session
3:
SRAM
&
Non-Volatile Memory [Grand Ballroom I]
3.1
A Quick Intelligent Program Architecture for
ЗУ-ОпІу
NAND-EEPROMS
T. Tanaka, Y. Tanaka, H. Nakamura, H. Oodaira, S. Aritome, R.Shirota,
F. Masuoka
.......................................................................................................................20
3.2
A New Decoding Scheme and Erase Sequence for 5V Only Sector
Erasable Flash Memory
T. Nakayama, S. Kobayashi, Y. Miyawaki, T. Futatsuya, Y. Terada, N.Ajika,
T. Yoshihara
.......................................................................................................................22
3.3
Serial 9Mb Flash
EEPROM
for Solid State Disk Applications
S. Mehrotra, J. Yuan, R.
Cernea,
W.
Chien,
D. Guterman, G.Samachisa,
R. Norman,
M.
Mofidi,
W.
Lee,
Y. Fong, A. Mihnea, E. Harari, R.
Gregor,
E.
Eberhardt,
J. Radosevich,
K.
Stiles,
R.
Kohier,
C.
Leung,
T. Mulrooney
...........................................................................24
3.4
A 6ns
1
Mb CMOS SRAM with High-Performance Sense Amplifier
T.
Sęki,
E.
lton,
С.
Furukawa,
I.
Maeno, T.
Ozawa,
H.
Sano,
N.
Suzuki,
Y.
Matsukawa
.........26
3.5
A Current-Mode Latch Sense Amplifier and a Static Power Saving
Input Buffer For Low-Power Architecture
T. Kobayashi, K.
Nogami,
T. Shirotori, Y.
Fujimoto, O.Watanabe
...........................................28
3.6
New Decoding Architecture to Reduce Peak Current and Its Implementation to
4M
ECL SRAM
A. Ohba, H. Sato. T. Hirose, A. Hosogane, H. Honda,
Y. Kohno
,
K.
Änami................................................................. 30
3.7
A 333MHz, 72Kb BiCMOS Pipelined Buffer Memory With Built-in Self Test
K. Yokonrzo, K. Naito
.......................................................... 32
vi · 1992
Symposium on VLSI Circuits Digest of Technical Papers
Session 4:
Integrated
Sensors [Grand
Ballroom
II]
4.1
A Low Cost Monolithic Accelerometer
S. Sherman, W. Tsang, T. Core, D. Quinn
...............................................................................34
4.2
Vertical Integration of Pyroelectric Detector Array and Integrated Signal
Processing Circuitry
L
Pham, W. Tjhen, T. Tamagawa, D.
Polla
.............................................................................36
4.3
A CCD/CMOS Based Imager with Integrated Focal Plane Signal Processing
С
Keasł,
С.
Sodini...................................................................................................................38
Session
5: Substrate
Noise and SOI Circuits [Grand Ballroom II]
5.1
Experimental Results and Modeling Techniques for Switching Noise in Mixed-Signal
Integrated Circuits
M. Loinaz,
D. Su,
В.
Wooley
....................................................................................................40
5.2
Simulation of Substrate Coupling in Mixed-Signal
MOS
Circuits
S. Masui
...................................................................................................................................42
5.3
Α ΙΰΗζ-Ο.θΓηΑ/ΐν
CMOS/SIMOX
+128/129
Dual Modulus Prescaler Using a Newly
Developed Counter
Y.
Kado,
M.
Suzuki,
К.
Koike,
Y.
Omura, K.
Izumi
...................................................................44
5.4 1
GHz
50
μνν
1/2
Frequency Divider Fabricated on Ultra-Thin
Simox
Substrate
M. Fujishima, M. Yamashita, M. Ikeda, K.
Asada, Y.
Omura, K.
Izumi,
T. Sakai, T.
Sugano
.................................................................................................................46
Rump
Sessions
R.1 Electronic Design
for Portability
R. Brodersen, K.
Fujishima
......................................................................................................48
R.2
Closing the Speed Gap Between CPU and DRAM
K.
Horninger,
N.
Lu..................................................................................................................
48
R.
3
Future
High-Speed Microprocessors
J.
Slager,
H. Edamatsu
............................................................................................................49
R.4 Flash Memory:
Future Prospects and Limitations
M
Winston,
J.
Miyamoto
.........................................................................................................49
Session
6:
Plenary Session II [Grand Ballrooms I
&
II]
6.1
Clocking Strategies in High Performance Processors
M. Horowitz
.............................................................................................................................50
6.2
Low Voltage ULSI Design
-
The Lower, the Better?
K. Shimohigashi, K. Seki
.........................................................................................................54
Session
7:
DRAM Innovations and Directions [Grand Ballrooms I
&
II]
7.1
Circuit Techniques for Multi-Bit Parallel Testing of
64Mb DRAMs
and Beyond
T
Sakuta, M. Muranaka, H. Matsuura, H. Tanaka, Y. Nakagome,
K. Míyazawa, M.
Ishihara
........................................................................................................60
7.2
Circuit Technologies for a 12ns
4Mb
TTL
BiCMOS DRAM at 3.3V Operation
Y. Yokoyama,
К
Nakagawa,
N.
Akiyama, T. Ohta, T. Someya, A.Tamba, H. Miyazawa,
K. Miyazawa.
J
Murata,
Y,
Kobayashi
....................................................................................62
7.3
A 35ns
64Mb
DRAM Using On-Chip Boosted Power Supply
D.-J. Lee, Y.-S. Seok, D.-C. Choi, J.-H. Lee, Y.-R. Kim, H.-S. Kim.D.-S.
Jun, O.-H.
Kwon
.....64
7.4 500
M
Byte/Sec Data-Rate
512
KBITS X
9
DRAM Using a Novel I/O Interface
N.
Kushiyama, S. Ohshima, D. Stark, K. Sakurai, S. Takase, T. Furuyama, R.
Barth,
J.
Dillon,
J
Gasbarro,
M
Griffin,
M.
Horowitz, V. Lee, W. Lee, W. Leung
...............................66
1992
Symposium on VLSI Circuits Digest of Technical Papers
·
vii
Session 8: Communications
Circuits
[Grand
Ballroom I]
8.1
A
9
Gbit/s Bandwidth Multiplexer/Demultiplexer CMOS Chip
A. Dunlop, T.
Gabara,
W.
Fischer
............................................................................................68
8.2
A Bipolar
1.5
Gb/s Monolithic Phase-Locked Loop for Clock and Data Extraction
J.-T. Wu, R.Walker
...............................................................................................................70
8.3
A 200-MHz Double-Sideband to Single-Sideband Converter in
1-μπι
CMOS
Generated by Silicon Compiler
R. Hawley, T.-J. Lin, H.
Samueli
..............................................................................................72
8.4
An
8
x
8
ATM Switch LSI with Shared Multi-Buffer Architecture
H. Notani, H. Kondoh, I. Hayashi,
H. Yamanaka, H. Saito, Y. Matsuda, M. Nakaya
................74
8.5
A
1.28
Gbps
16x16
CMOS Chip Set for an Output-Buffer ATM Switch
N.
Sugaya, H. Nagano, T. Morita, S. Kawanago, R. Kuriki, M. Sakamoto, T. Suzuki
..............76
8.6
A Si Bipolar
1.4
GHz Time Space Switch LSI FOR B-ISDN
O. Matsuda, S.-l. Hayano, T. Takeuchi, H. Kitahata, H.
Takemura, T. Tashiro
.......................78
Session
9:
Circuit Techniques [Grand Ballroom II]
9.1
High-Speed Low-Power Darlington ECL Circuit
С
Chuang, K. Chin, P.
Lu
and H. Shin
....................................................................................80
9.2
Sub-1-V Swing Bus Architecture for Future Low-Power ULSIs
Y. Nakagome, K. Itoh, M. Isoda, K. Takeuchi, M. Aoki
...........................................................82
9.3
A Dual
PLL
Based
Multi
Frequency Clock Distribution Scheme
A. Thaik, H.-N. Nguyen
............................................................................................................84
9.4
A
1
Mbit NAND-Type Content Addressable ROM with a Variable-Length
Match Function
M. Yoneda, H. Sasama, I. Hayashibara,
N.
Kanazawa
..........................................................86
9.5
А О.бцт
CMOS
SOG
with 5V/3.3V Interfaces
M. Ohkawa, T. Takahashi, M. Yamagishi, Y. Sonobe,
N.
Ejima
..............................................88
9.6
Highly Reliable Process Insensitive 3.3V-5V Interface Circuit
Y.
Wada,
J.
Gotoh,
H.
Takakura, T. lida,
T.
Noguchi
...............................................................90
Session
10:
Data
Converters and Filters [Grand Ballroom I]
10.1
A 10BIT 50MS/S CMOS
D/A
Converter with 2.7V Power Supply
T.
Miki,
Y.
Nakamura,
Y.
Nishikawa,
K. Okada, Y. Honba
.......................................................92
10.2
A 10b 300MHz Interpolated-Parallel A/D Converter
H. Kimura, A. Matsuzawa, T. Nakamura, S. Sawada
..............................................................94
10.3
A High-Speed Parallel Pipelined ADC Technique in CMOS
С
Conroy, D.
Cline,
P. Gray
....................................................................................................96
10.4
A 95-mW, 10-b 15-MHz Low-Power CMOS ADC Using Analog Double-Sampled
Pipelining Scheme
T. Matsuura, M. Hotta.
К
Usui, E.
Imaizumi,
S.
(Jeda
.............................................................98
10.5
A Low Power 12-b Analog-to-Digital Converter With On-Chip Precision Trimming
M, deWit, K.-S. Tan, R. Hester
.............................................................................................100
10.6
An Interpolative Bandpass Converter on
a
1.2μηι
BiCMOS Analog/Digital Array
G
Troester, P. Sieber,
К
Schoppe,
A
Wedel,
E. Zocher, J.
Arndt,
H.-J.
Dressler,
H.-J. Golberg, W. Schardein
..................................................................................................102
10.7
A 20MHz 6th Order
BiCMOS
Programmable
Filter
Using Parasitic- Insensitive
Integrators
С.
Laber,
P. Gray
...................................................................................................................104
Session
11 :
New Circuit Techniques for
DRAMs
[Grand Ballroom II]
11.1
Application of a High-Voltage Pumped Supply for Low-Power DRAM
R.
Foss.
G.
Allan. P.
Gillingham,
F. Larochelle,
V. Lines,
G
Shimokura
...............................106
viii · 1992
Symposium on VLSI Circuits Digest of Technical Papers
11.2
A New On-Chip Voltage Regulator for High Density CMOS DRAMS
R. Mao, H.
Chao, Y.
Chi, P. Chung,
C. Hsieh, C. Lin,
N.
Lu, S. Lan, Y. Liu, M. Lin,
D. Wang, H. Tuan, H. Tsai,
С
Lu
..........................................................................................108
11.3
Variable Vcc Design Techniques
for Battery Operated DRAMS
S.-M. Yoo, E. Haq, S.-H. Lee, Y.-H.
Choi,
S.-l. Cho, N.-S. Kang, D.
Chin
.............................110
11.4
A
Boosted Dual Word-Line Decoding Scheme for
256Mb
DRAMS
К.
Noda,
T.
Saeki, A. Tsujimoto, T. Murotani, K. Koyama
.....................................................112
11.5
Low Power On-Chip Supply Voltage Conversion Scheme for
1
G/4G BIT DRAMS
D. Takashima, S. Watanabe, T. Fuse, K. Sunouchi,
Т. Нага
.................................................114
11.6
Offset Compensating Bit-Line Sensing Scheme for High Density DRAMS
Y. Watanabe,
N.
Nakamura, D. Takashima, T.
Hara,
S.
Watanabe
......................................116
Author Index
....................................................................................................................................118
1992
Symposium on VLSI Circuits Digest of Technical Papers
· ix
|
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| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 1992 Seattle Wash. gnd-content |
| genre_facet | Konferenzschrift 1992 Seattle Wash. |
| id | DE-604.BV009584766 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T17:37:31Z |
| institution | BVB |
| institution_GND | (DE-588)5079964-2 |
| isbn | 0780307011 078030702X 0780307038 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006334738 |
| oclc_num | 26776819 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-83 |
| owner_facet | DE-91 DE-BY-TUM DE-83 |
| physical | X, 120 S. Ill., graph. Darst. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| publisher | IEEE Service Center |
| record_format | marc |
| spelling | Symposium on VLSI Circuits 6 1992 Seattle, Wash. Verfasser (DE-588)5079964-2 aut Digest of technical papers Symposium on VLSI Circuits 1992 ; IEEE Solid-State Circuits Council Piscataway, NJ IEEE Service Center 1992 X, 120 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Computers Circuits Congresses Integrated circuits Very large scale integration Congresses Halbleitertechnologie (DE-588)4158814-9 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1992 Seattle Wash. gnd-content Integrierte Schaltung (DE-588)4027242-4 s VLSI (DE-588)4117388-0 s DE-604 Halbleitertechnologie (DE-588)4158814-9 s 1\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006334738&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Digest of technical papers Computers Circuits Congresses Integrated circuits Very large scale integration Congresses Halbleitertechnologie (DE-588)4158814-9 gnd Integrierte Schaltung (DE-588)4027242-4 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4158814-9 (DE-588)4027242-4 (DE-588)4117388-0 (DE-588)1071861417 |
| title | Digest of technical papers |
| title_auth | Digest of technical papers |
| title_exact_search | Digest of technical papers |
| title_full | Digest of technical papers Symposium on VLSI Circuits 1992 ; IEEE Solid-State Circuits Council |
| title_fullStr | Digest of technical papers Symposium on VLSI Circuits 1992 ; IEEE Solid-State Circuits Council |
| title_full_unstemmed | Digest of technical papers Symposium on VLSI Circuits 1992 ; IEEE Solid-State Circuits Council |
| title_short | Digest of technical papers |
| title_sort | digest of technical papers |
| topic | Computers Circuits Congresses Integrated circuits Very large scale integration Congresses Halbleitertechnologie (DE-588)4158814-9 gnd Integrierte Schaltung (DE-588)4027242-4 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Computers Circuits Congresses Integrated circuits Very large scale integration Congresses Halbleitertechnologie Integrierte Schaltung VLSI Konferenzschrift 1992 Seattle Wash. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006334738&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT symposiumonvlsicircuitsseattlewash digestoftechnicalpapers |