ICMTS 92: proceedings of the 1992 International Conference on Microelectronic Test Structures ; March 16 - 19, 1992, San Diego, California
Gespeichert in:
| Format: | Tagungsbericht Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Piscataway, NJ
IEEE Service Center
1992
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XI, 214 S. Ill., graph. Darst. |
| ISBN: | 0780305353 0780305361 078030537X |
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Datensatz im Suchindex
| _version_ | 1804123925155676160 |
|---|---|
| adam_text | SESSION
I
TEST
STRUCTURES FOR RELIABILITY
PREDICTION AND ANALYSIS
.................................................1-23
Capacitor Insulator Reliability Prediction Using Three-Dimensional
Test Chips for
Submicron
DRAMS
.......................................................................................................................1
/.
Yugami, T. Mine,
S. Ujíma,
and
A.
Hiraiwa, Hitachi Ltd., Japan
CMOS-ASIC Life-Predictions from Test-Coupon Data
...................................................................................6
M.G. Buehler,
N.
Zamani, and
JA.
Zoutendyk,
Jet Propulsion Laboratory, USA
Finite Element Analysis of a Sweat Structure with a
3-D,
Nonlinear,
Coupled Thermal-electric Model
.......................................................................................................................12
M J.
Dion, SEMATECH, USA
A New Latch-up Test Structure for Practical Design Methodology
for Internal Circuits in Standard-Cell-Based CMOS/BiCMOS LSIs
............................................................18
T. Aoki, NTT LSI Laboratories, Japan
SESSION
Π
DEVICE AND PROCESS CHARACTERIZATION
.............................24-43
A Novel Test Structure for Monitoring Technological
Mismatches in DRAM Processes
.........................................................................................................................24
H. Geib, W. Weber, and L. Risch, Siemens
AG,
Germany
A Simple Method to Measure Very Low Currents to Evaluate the Effect of Damage
Caused by Contact Formation Near the Isolation Edges in High-Density LSI s
........................................30
J. Matsuda and
Y. Oba,
Sanyo Electric Co., Ltd., Japan
Two-Dimensional Current/Voltage Measurements of
Reverse-Biased n+- Diodes by
Photoemission ..................................................................................................34
T.
Ohzone and H. Iwata, Toyama Prefectural University, Japan
Test Structures for Analysis and Parameter Extraction of Secondary
Photon-Induced Leakage Currents in CMOS DRAM Technology
.................................................................39
S.H. Voldman, IBM, USA
SESSION III
DEFECT ANALYSIS AND YIELD MANAGEMENT
...........................44-56
A Study of Clustering Using Microelectronic Defect Monitors
.................... 44
A.V.S. Satya, IBM, USA
Yield Test Structures and Their Use for Process Development
.................... 47
S.
Magdo,
IBM, USA
ii
Issues
with
Contact Defect
Test Structures
......................................................................................................53
MA.
Mitchell,
L.
Forner,
and J.
Huang, Honeywell, USA
SESSION IV
CAPACITANCE MEASUREMENT EXTRACTION
.............................57-72
Accurate Determination of CMOS Capacitance Parameters
Using Multilayer Structures
.............................................................................................................................57
W.
de Lange,
Intergraph Corp., USA
A New Method and Test Structure for Easy Determination of Femto-Farad
On-Chip Capacitances in an
MOS
Process
.......................................................................................................62
B.
Laquai, H.
Richter,
and
В.
Hofflinger,
Institute for Microelectronics, Stuttgart, Germany
Inverse Modeling for Doping Profile Extraction in the Presence of Interface Traps
..................................67
K. Iniewski, University of Toronto, Canada
SESSION V
MODELING PARAMETER EXTRACTION I
..................................73-93
Effective Channel Length Determination Using Punchthrough Voltage
......................................................73
S. Nakanishi, M.
Höljer,
Y.
Saitoh,
Y.
Katoh,
Y.
Kojima,
and
M.
Kamiya,
SEIKO Instruments Inc., Japan
An Analytical Strategy for Fast Extraction of
MOS
Transistor DC Parameters
Applied to the Spice MOS3 and the BSIM Models
..........................................................................................78
PR.
Karlsson
and
К.О.
Jeppson, Chalmers University of Technology, Sweden
Dependence of Spice Level
3
Model Parameters with Transistor Size
.........................................................84
C.
Perelló,
M.
Lozano,
С.
Cane, and E.
Lora-Tamayo,
University of
Barcelona,
Spain
Test Structures and Measurement Techniques for the Characterization of the
Dynamic Behaviour of CMOS Transistors on a Wafer in the GHz Range
..................................................90
J.
Hänseier,
H.
Schinagel,
and
H.L.
Zapf, Seimens
AG,
Germany
SESSION VI
HOT CARRIER RELIABILITY ISSUES
....................................94-114
Life Time Evaluation of MOSFETs in ULSI Circuits Using Photon Emission Method
.............................94
N.
Tsutsu, Y. Uraoka, T.
Morii,
and
K. Tsuji,
Matsushita Electric Industrial Co., Ltd., Japan
New Failure Analysis Technique of ULSI Circuits Using Photon Emission Method
................................100
Y. Uraoka, I. Miyanaga, T. Maeda, and K. Tsuji,
Matsushita Electric Industrial Co., Ltd., Japan
iii
The Design, Fabrication, and Measurements of Asymmetrical LDD Transistors
.....................................106
R.C. Smith and AJ. Walton, Edinburgh University, Scotland
Test Structure and Experimental Analysis of Bipolar
Hot-Carrier Degradation Including Stress Field Effect
..............................................................................
Ill
H. Shimamoto, M. Tanabe, T.
Orni,
К.
Washio, and T. Nakamwa,
Hitachi Device Engineering Co., Ltd., Japan
SESSION
POSTER SESSION
........................................................115-173
Three-Dimensional Effects of Latchup Turn-On CMOS and
Forward-Biased N+-Diode Measured by
Photoemission ...............................................................................115
Г.
Ohzone and H.
¡wata,
Toyama Prefectural University, Japan
Carrier Transport Test Structure for Characterization
of Poly-ZMonosilicon Interfaces
.......................................................................................................................121
B. Ни,
H.H.
Berger,
A. Gauckler, and
В.
Muller,
Technical University of Berlin, Germany
A New Method for Electrically Measuring Thin-Film Thickness of SOI MOSFETS
...............................125
H. Yamazaki, S.
Ando,
Η.
Horie, and
S.
Hijiya,
Fujitsu Laboratories Ltd., Japan
The Use of a Digital Multiplexer to Reduce Process Control Chip Pad Count
..........................................129
D. Ward, AJ. Walton, W.G.
Gammie,
and
RJ.
Holwill,
University of Edinburgh, Scotland
A New and Simple Test Structure for Evaluating Sectional Photosensitivity
Distribution of Pixels in a Frame Transfer
CCD
Image Sensor
..................................................................134
M. Okigawa, Sanyo Electric Co. Ltd., Japan
Test Structure for the Detection, Localization, and Identification of Short
Circuits with a High Speed Digital Tester
.....................................................................................................139
C. Hess, L.H.
Weiland,
and
D.
Schmid,
University of Karlsruhe, Germany
Automatic Test Chip and Test Program Generation: An Approach to
Parametric Test Computer-Aided Design
......................................................................................................145
T. Ternisien d OuvillcJ-P. Jeanne, andJL.
Leder
xq, CNET, andD. CaloudandL.
Zangara,
Dolphin Integration, France
A High-Speed TEG Evaluation System Integrating Parallel/Continuous
Processing Software and High-Speed Hardware
...........................................................................................150
K. Kubota, T. Takeda, and T.
Saturai,
NTT LSI Laboratories, Japan
Test Structures for ISFET Chemical Sensors
................................................................................................156
/.
Grácia, C.
Cane, M.
Lozano,
and J.
Esteve,
Universität
Autònoma de
Barcelona,
Spain
IV
A Modular
0.7
μιη
CMOS JESSI Test Chip for
Multi
Purpose Applications
..........................................160
T. Brenner,
N.
Maene, and E. Janssens, Alcatel; S.
Lindenkreuz,
Robert Bosch GmbH; J.
le Ber,
Bull
SA; H.
Richter, Institute
for Microelectronics,
Stuttgart;
G.
Morin, SGS-Thomson;
and J.
Hänseier, Siemens AG,
Germany
An
Optical Measurement Method for PN Junction Depth
..........................................................................166
H.
Yie, and S. Yafei, Southeast University, China
Note on Designing a Comprehensive Electron Scanning Microscopy Test Structure
...............................170
K. Golshan,
M. Harward, and H. Tigelaar, Texas Instruments, USA
SESSION
TEST STRUCTURES FOR DIMENSIONAL MEASUREMENTS
............174-195
Voltage-Dividing Potentiometer Enhancements for High-Precision
Feature Placement Metrology
........................................................................................................................174
R
A. Allen, M.W. Cresswell, C.H.
Ellenwood,
and
L.W.
Linholm,
National Institute of Standards and Technology, USA
Critical Dimension Measurements by Electron and Optical Beams for
Establishment of Linewidth Standards
.........................................................................................................180
T. Hatsuzawa and K. Toy
oda, MITI,
Japan
VLSI Interconnect Linewidth Variation: A Method to Characterize Depth
of Focus and Proximity Effects
.......................................................................................................................185
PJ. Wright, E. Burke, and
A. Appel,
Texas Instruments, USA
Extracting Contact Misalignment From
4-
and 6-Terminal Contact Resistors
........................................190
U. Lieneweg andH.R. Sayah, Jet Propulsion Laboratory, USA
SESSION IX
MODELING PARAMETER EXTRACTION
Π
...............................196-212
Measurements and Parameter Extraction of Sub-Micron VLSI MOSFET
Test Structures
..................................................................................................................................................196
CS.
Wen, M. Guldahl, and
L
JR. Sadwick,
University of Utah, R. Kent, Intel Corporation, andH. Gaffur,
National Semiconductor, USA
An Investigation of MOSFET Statistical and Temperature Effects
............................................................202
JA.
Power, R. Clancy,
W
A. Wall, A. Mathewson, and
WA.
Lane,
University College Cork, Ireland
Suppression of Measurement Errors in Effective
MOSFET-Channel-Length Extraction
...........................................................................................................208
K. Terada, NEC Corporation, Japan
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| illustrated | Illustrated |
| indexdate | 2024-07-09T17:37:30Z |
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| spelling | ICMTS 92 proceedings of the 1992 International Conference on Microelectronic Test Structures ; March 16 - 19, 1992, San Diego, California Piscataway, NJ IEEE Service Center 1992 XI, 214 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Integrated circuits Testing Congresses Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Testen (DE-588)4367264-4 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1992 San Diego Calif. gnd-content Integrierte Schaltung (DE-588)4027242-4 s Testen (DE-588)4367264-4 s DE-604 ICMTS 5 1992 San Diego, Calif. Sonstige (DE-588)5084378-3 oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006334405&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | ICMTS 92 proceedings of the 1992 International Conference on Microelectronic Test Structures ; March 16 - 19, 1992, San Diego, California Integrated circuits Testing Congresses Integrierte Schaltung (DE-588)4027242-4 gnd Testen (DE-588)4367264-4 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4367264-4 (DE-588)1071861417 |
| title | ICMTS 92 proceedings of the 1992 International Conference on Microelectronic Test Structures ; March 16 - 19, 1992, San Diego, California |
| title_auth | ICMTS 92 proceedings of the 1992 International Conference on Microelectronic Test Structures ; March 16 - 19, 1992, San Diego, California |
| title_exact_search | ICMTS 92 proceedings of the 1992 International Conference on Microelectronic Test Structures ; March 16 - 19, 1992, San Diego, California |
| title_full | ICMTS 92 proceedings of the 1992 International Conference on Microelectronic Test Structures ; March 16 - 19, 1992, San Diego, California |
| title_fullStr | ICMTS 92 proceedings of the 1992 International Conference on Microelectronic Test Structures ; March 16 - 19, 1992, San Diego, California |
| title_full_unstemmed | ICMTS 92 proceedings of the 1992 International Conference on Microelectronic Test Structures ; March 16 - 19, 1992, San Diego, California |
| title_short | ICMTS 92 |
| title_sort | icmts 92 proceedings of the 1992 international conference on microelectronic test structures march 16 19 1992 san diego california |
| title_sub | proceedings of the 1992 International Conference on Microelectronic Test Structures ; March 16 - 19, 1992, San Diego, California |
| topic | Integrated circuits Testing Congresses Integrierte Schaltung (DE-588)4027242-4 gnd Testen (DE-588)4367264-4 gnd |
| topic_facet | Integrated circuits Testing Congresses Integrierte Schaltung Testen Konferenzschrift 1992 San Diego Calif. |
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