Timing optimization of multi-phase sequential logic:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Seattle, Wash.
1989
|
| Schriftenreihe: | University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report
89,12,5 |
| Schlagworte: | |
| Beschreibung: | 11 S. |
Internformat
MARC
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| 100 | 1 | |a Bartlett, Karen |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Timing optimization of multi-phase sequential logic |c Karen Bartlett ; Gaetano Borriello ; Sitaram Raju |
| 264 | 1 | |a Seattle, Wash. |c 1989 | |
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| 490 | 1 | |a University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report |v 89,12,5 | |
| 650 | 4 | |a Integrated circuits |x Design | |
| 700 | 1 | |a Borriello, Gaetano |e Verfasser |4 aut | |
| 700 | 1 | |a Raju, Sitaram |e Verfasser |4 aut | |
| 810 | 2 | |a Department of Computer Science: Technical report |t University of Washington <Seattle, Wash.> |v 89,12,5 |w (DE-604)BV008930431 |9 89,12,5 | |
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Datensatz im Suchindex
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| any_adam_object | |
| author | Bartlett, Karen Borriello, Gaetano Raju, Sitaram |
| author_facet | Bartlett, Karen Borriello, Gaetano Raju, Sitaram |
| author_role | aut aut aut |
| author_sort | Bartlett, Karen |
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| building | Verbundindex |
| bvnumber | BV009260371 |
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| id | DE-604.BV009260371 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:34:04Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006162247 |
| oclc_num | 27920946 |
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| owner | DE-29T |
| owner_facet | DE-29T |
| physical | 11 S. |
| publishDate | 1989 |
| publishDateSearch | 1989 |
| publishDateSort | 1989 |
| record_format | marc |
| series2 | University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report |
| spelling | Bartlett, Karen Verfasser aut Timing optimization of multi-phase sequential logic Karen Bartlett ; Gaetano Borriello ; Sitaram Raju Seattle, Wash. 1989 11 S. txt rdacontent n rdamedia nc rdacarrier University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report 89,12,5 Integrated circuits Design Borriello, Gaetano Verfasser aut Raju, Sitaram Verfasser aut Department of Computer Science: Technical report University of Washington <Seattle, Wash.> 89,12,5 (DE-604)BV008930431 89,12,5 |
| spellingShingle | Bartlett, Karen Borriello, Gaetano Raju, Sitaram Timing optimization of multi-phase sequential logic Integrated circuits Design |
| title | Timing optimization of multi-phase sequential logic |
| title_auth | Timing optimization of multi-phase sequential logic |
| title_exact_search | Timing optimization of multi-phase sequential logic |
| title_full | Timing optimization of multi-phase sequential logic Karen Bartlett ; Gaetano Borriello ; Sitaram Raju |
| title_fullStr | Timing optimization of multi-phase sequential logic Karen Bartlett ; Gaetano Borriello ; Sitaram Raju |
| title_full_unstemmed | Timing optimization of multi-phase sequential logic Karen Bartlett ; Gaetano Borriello ; Sitaram Raju |
| title_short | Timing optimization of multi-phase sequential logic |
| title_sort | timing optimization of multi phase sequential logic |
| topic | Integrated circuits Design |
| topic_facet | Integrated circuits Design |
| volume_link | (DE-604)BV008930431 |
| work_keys_str_mv | AT bartlettkaren timingoptimizationofmultiphasesequentiallogic AT borriellogaetano timingoptimizationofmultiphasesequentiallogic AT rajusitaram timingoptimizationofmultiphasesequentiallogic |