Memory hierarchy management schemes in large scale shared-memory multiprocessors:
Abstract: "The speed of access to shared global memory is one of the most important aspects, if not the most important one, in the performance of any shared-memory multiprocessor. Shared-memory multiprocessors with a multistage interconnection network, systems that are known to be both scalable...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Seattle, Wash.
1989
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| Schriftenreihe: | University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report
89,8,7 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "The speed of access to shared global memory is one of the most important aspects, if not the most important one, in the performance of any shared-memory multiprocessor. Shared-memory multiprocessors with a multistage interconnection network, systems that are known to be both scalable and cost-effective, have two important weaknesses: slow access to global memory and the absence of an instantaneous broadcast mechanism. In this dissertation we propose ways of managing memory hierarchies in such an environment to cope with these weaknesses. Slow access to global memory can be alleviated by associating private caches with the processing elements. However, this gives rise to the cache coherence problem We propose a timestamp-based self-invalidation cache coherence scheme that allows the exploration of localities across different computational units and show that it performs significantly better than the previous schemes with no or limited such ability. This scheme does not require any shared resource (e.g., sophisticated memory controllers) and is not affected by the absence of an instantaneous broadcast mechanism. Compile-time optimizations which are aimed at increasing the effectiveness of the memory hierarchy are proposed assuming the presence of the timestamp-based cache coherence scheme. We also propose architectural enhancements in the form of super registers which are registers embedded in the interconnection network These super registers are shared by a proper subset of the processors to reduce the average access time of shared variables with known access patterns. |
| Beschreibung: | Zugl.: Washington, DC, Univ., Diss. |
| Beschreibung: | X, 200 S. |
Internformat
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| 100 | 1 | |a Min, Sang L. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Memory hierarchy management schemes in large scale shared-memory multiprocessors |c Sang Lyul Min |
| 264 | 1 | |a Seattle, Wash. |c 1989 | |
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| 490 | 1 | |a University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report |v 89,8,7 | |
| 500 | |a Zugl.: Washington, DC, Univ., Diss. | ||
| 520 | 3 | |a Abstract: "The speed of access to shared global memory is one of the most important aspects, if not the most important one, in the performance of any shared-memory multiprocessor. Shared-memory multiprocessors with a multistage interconnection network, systems that are known to be both scalable and cost-effective, have two important weaknesses: slow access to global memory and the absence of an instantaneous broadcast mechanism. In this dissertation we propose ways of managing memory hierarchies in such an environment to cope with these weaknesses. Slow access to global memory can be alleviated by associating private caches with the processing elements. However, this gives rise to the cache coherence problem | |
| 520 | 3 | |a We propose a timestamp-based self-invalidation cache coherence scheme that allows the exploration of localities across different computational units and show that it performs significantly better than the previous schemes with no or limited such ability. This scheme does not require any shared resource (e.g., sophisticated memory controllers) and is not affected by the absence of an instantaneous broadcast mechanism. Compile-time optimizations which are aimed at increasing the effectiveness of the memory hierarchy are proposed assuming the presence of the timestamp-based cache coherence scheme. We also propose architectural enhancements in the form of super registers which are registers embedded in the interconnection network | |
| 520 | 3 | |a These super registers are shared by a proper subset of the processors to reduce the average access time of shared variables with known access patterns. | |
| 650 | 4 | |a Computer storage devices | |
| 650 | 4 | |a Multiprocessors | |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 810 | 2 | |a Department of Computer Science: Technical report |t University of Washington <Seattle, Wash.> |v 89,8,7 |w (DE-604)BV008930431 |9 89,8,7 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-006160353 | ||
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| author | Min, Sang L. |
| author_facet | Min, Sang L. |
| author_role | aut |
| author_sort | Min, Sang L. |
| author_variant | s l m sl slm |
| building | Verbundindex |
| bvnumber | BV009258297 |
| ctrlnum | (OCoLC)23932816 (DE-599)BVBBV009258297 |
| format | Book |
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| indexdate | 2024-07-09T17:34:01Z |
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| language | English |
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| physical | X, 200 S. |
| publishDate | 1989 |
| publishDateSearch | 1989 |
| publishDateSort | 1989 |
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| series2 | University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report |
| spelling | Min, Sang L. Verfasser aut Memory hierarchy management schemes in large scale shared-memory multiprocessors Sang Lyul Min Seattle, Wash. 1989 X, 200 S. txt rdacontent n rdamedia nc rdacarrier University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report 89,8,7 Zugl.: Washington, DC, Univ., Diss. Abstract: "The speed of access to shared global memory is one of the most important aspects, if not the most important one, in the performance of any shared-memory multiprocessor. Shared-memory multiprocessors with a multistage interconnection network, systems that are known to be both scalable and cost-effective, have two important weaknesses: slow access to global memory and the absence of an instantaneous broadcast mechanism. In this dissertation we propose ways of managing memory hierarchies in such an environment to cope with these weaknesses. Slow access to global memory can be alleviated by associating private caches with the processing elements. However, this gives rise to the cache coherence problem We propose a timestamp-based self-invalidation cache coherence scheme that allows the exploration of localities across different computational units and show that it performs significantly better than the previous schemes with no or limited such ability. This scheme does not require any shared resource (e.g., sophisticated memory controllers) and is not affected by the absence of an instantaneous broadcast mechanism. Compile-time optimizations which are aimed at increasing the effectiveness of the memory hierarchy are proposed assuming the presence of the timestamp-based cache coherence scheme. We also propose architectural enhancements in the form of super registers which are registers embedded in the interconnection network These super registers are shared by a proper subset of the processors to reduce the average access time of shared variables with known access patterns. Computer storage devices Multiprocessors (DE-588)4113937-9 Hochschulschrift gnd-content Department of Computer Science: Technical report University of Washington <Seattle, Wash.> 89,8,7 (DE-604)BV008930431 89,8,7 |
| spellingShingle | Min, Sang L. Memory hierarchy management schemes in large scale shared-memory multiprocessors Computer storage devices Multiprocessors |
| subject_GND | (DE-588)4113937-9 |
| title | Memory hierarchy management schemes in large scale shared-memory multiprocessors |
| title_auth | Memory hierarchy management schemes in large scale shared-memory multiprocessors |
| title_exact_search | Memory hierarchy management schemes in large scale shared-memory multiprocessors |
| title_full | Memory hierarchy management schemes in large scale shared-memory multiprocessors Sang Lyul Min |
| title_fullStr | Memory hierarchy management schemes in large scale shared-memory multiprocessors Sang Lyul Min |
| title_full_unstemmed | Memory hierarchy management schemes in large scale shared-memory multiprocessors Sang Lyul Min |
| title_short | Memory hierarchy management schemes in large scale shared-memory multiprocessors |
| title_sort | memory hierarchy management schemes in large scale shared memory multiprocessors |
| topic | Computer storage devices Multiprocessors |
| topic_facet | Computer storage devices Multiprocessors Hochschulschrift |
| volume_link | (DE-604)BV008930431 |
| work_keys_str_mv | AT minsangl memoryhierarchymanagementschemesinlargescalesharedmemorymultiprocessors |