Retiming synchronous circuitry:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Palo Alto, Calif.
1986
|
| Schriftenreihe: | Systems Research Center <Palo Alto, Calif.>: SRC reports
13 |
| Schlagworte: | |
| Beschreibung: | 42 S. |
Internformat
MARC
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| 264 | 1 | |a Palo Alto, Calif. |c 1986 | |
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| 490 | 1 | |a Systems Research Center <Palo Alto, Calif.>: SRC reports |v 13 | |
| 650 | 4 | |a Circuits intégrés à très grande échelle - Conception et construction | |
| 650 | 4 | |a Ordinateurs - Circuits - Conception et construction | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration | |
| 650 | 4 | |a Synchronization | |
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Datensatz im Suchindex
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| author | Leiserson, Charles E. Saxe, James B. |
| author_facet | Leiserson, Charles E. Saxe, James B. |
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| ctrlnum | (OCoLC)14706689 (DE-599)BVBBV009245880 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV009245880 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:33:49Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006152224 |
| oclc_num | 14706689 |
| open_access_boolean | |
| owner | DE-29T |
| owner_facet | DE-29T |
| physical | 42 S. |
| publishDate | 1986 |
| publishDateSearch | 1986 |
| publishDateSort | 1986 |
| record_format | marc |
| series | Systems Research Center <Palo Alto, Calif.>: SRC reports |
| series2 | Systems Research Center <Palo Alto, Calif.>: SRC reports |
| spelling | Leiserson, Charles E. Verfasser aut Retiming synchronous circuitry by Charles E. Leiserson and James B. Saxe Palo Alto, Calif. 1986 42 S. txt rdacontent n rdamedia nc rdacarrier Systems Research Center <Palo Alto, Calif.>: SRC reports 13 Circuits intégrés à très grande échelle - Conception et construction Ordinateurs - Circuits - Conception et construction Integrated circuits Very large scale integration Synchronization Kombinatorische Optimierung (DE-588)4031826-6 gnd rswk-swf Graph (DE-588)4021842-9 gnd rswk-swf Algorithmus (DE-588)4001183-5 gnd rswk-swf Algorithmus (DE-588)4001183-5 s DE-604 Graph (DE-588)4021842-9 s Kombinatorische Optimierung (DE-588)4031826-6 s Saxe, James B. Verfasser aut Systems Research Center <Palo Alto, Calif.>: SRC reports 13 (DE-604)BV006187016 13 |
| spellingShingle | Leiserson, Charles E. Saxe, James B. Retiming synchronous circuitry Systems Research Center <Palo Alto, Calif.>: SRC reports Circuits intégrés à très grande échelle - Conception et construction Ordinateurs - Circuits - Conception et construction Integrated circuits Very large scale integration Synchronization Kombinatorische Optimierung (DE-588)4031826-6 gnd Graph (DE-588)4021842-9 gnd Algorithmus (DE-588)4001183-5 gnd |
| subject_GND | (DE-588)4031826-6 (DE-588)4021842-9 (DE-588)4001183-5 |
| title | Retiming synchronous circuitry |
| title_auth | Retiming synchronous circuitry |
| title_exact_search | Retiming synchronous circuitry |
| title_full | Retiming synchronous circuitry by Charles E. Leiserson and James B. Saxe |
| title_fullStr | Retiming synchronous circuitry by Charles E. Leiserson and James B. Saxe |
| title_full_unstemmed | Retiming synchronous circuitry by Charles E. Leiserson and James B. Saxe |
| title_short | Retiming synchronous circuitry |
| title_sort | retiming synchronous circuitry |
| topic | Circuits intégrés à très grande échelle - Conception et construction Ordinateurs - Circuits - Conception et construction Integrated circuits Very large scale integration Synchronization Kombinatorische Optimierung (DE-588)4031826-6 gnd Graph (DE-588)4021842-9 gnd Algorithmus (DE-588)4001183-5 gnd |
| topic_facet | Circuits intégrés à très grande échelle - Conception et construction Ordinateurs - Circuits - Conception et construction Integrated circuits Very large scale integration Synchronization Kombinatorische Optimierung Graph Algorithmus |
| volume_link | (DE-604)BV006187016 |
| work_keys_str_mv | AT leisersoncharlese retimingsynchronouscircuitry AT saxejamesb retimingsynchronouscircuitry |