Design systems for VLSI circuits: logic synthesis and silicon compilation ; [proceedings of the NATO Advanced Study Inst. on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7 - 18, 1986]
Gespeichert in:
Format: | Tagungsbericht Buch |
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Sprache: | Undetermined |
Veröffentlicht: |
Dordrecht u.a.
Nijhoff
1987
|
Schriftenreihe: | NATO: NATO ASI series / E
136 |
Schlagworte: | |
Beschreibung: | VIII, 651 S. |
ISBN: | 9024735610 9024735629 |
Internformat
MARC
LEADER | 00000nam a2200000 cb4500 | ||
---|---|---|---|
001 | BV009226699 | ||
003 | DE-604 | ||
007 | t| | ||
008 | 940313s1987 xx |||| 10||| und d | ||
020 | |a 9024735610 |9 90-247-3561-0 | ||
020 | |a 9024735629 |9 90-247-3562-9 | ||
035 | |a (OCoLC)632600138 | ||
035 | |a (DE-599)BVBBV009226699 | ||
040 | |a DE-604 |b ger |e rakddb | ||
041 | |a und | ||
049 | |a DE-29T | ||
084 | |a ZN 4952 |0 (DE-625)157425: |2 rvk | ||
245 | 1 | 0 | |a Design systems for VLSI circuits |b logic synthesis and silicon compilation ; [proceedings of the NATO Advanced Study Inst. on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7 - 18, 1986] |c ed. by G. De Micheli |
264 | 1 | |a Dordrecht u.a. |b Nijhoff |c 1987 | |
300 | |a VIII, 651 S. | ||
336 | |b txt |2 rdacontent | ||
337 | |b n |2 rdamedia | ||
338 | |b nc |2 rdacarrier | ||
490 | 1 | |a NATO: NATO ASI series / E |v 136 | |
650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Logischer Entwurf |0 (DE-588)4168051-0 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Mathematische Methode |0 (DE-588)4155620-3 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 1986 |z L'Aquila |2 gnd-content | |
689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
689 | 0 | 1 | |a Logischer Entwurf |0 (DE-588)4168051-0 |D s |
689 | 0 | |5 DE-604 | |
689 | 1 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
689 | 1 | 1 | |a Entwurf |0 (DE-588)4121208-3 |D s |
689 | 1 | |8 1\p |5 DE-604 | |
689 | 2 | 0 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
689 | 2 | |8 2\p |5 DE-604 | |
689 | 3 | 0 | |a Mathematische Methode |0 (DE-588)4155620-3 |D s |
689 | 3 | |8 3\p |5 DE-604 | |
700 | 1 | |a De Micheli, Giovanni |d 1955- |e Sonstige |0 (DE-588)114063575 |4 oth | |
711 | 2 | |a Advanced Study Institute on Logic Synthesis and Silicon Compilation for VLSI Design |d 1986 |c L'Aquila |j Sonstige |0 (DE-588)806439-8 |4 oth | |
810 | 2 | |a E |t NATO: NATO ASI series |v 136 |w (DE-604)BV000007015 |9 136 | |
883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
883 | 1 | |8 3\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-006135487 |
Datensatz im Suchindex
_version_ | 1820868047095726080 |
---|---|
adam_text | |
any_adam_object | |
author_GND | (DE-588)114063575 |
building | Verbundindex |
bvnumber | BV009226699 |
classification_rvk | ZN 4952 |
ctrlnum | (OCoLC)632600138 (DE-599)BVBBV009226699 |
discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
format | Conference Proceeding Book |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000 cb4500</leader><controlfield tag="001">BV009226699</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">940313s1987 xx |||| 10||| und d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9024735610</subfield><subfield code="9">90-247-3561-0</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9024735629</subfield><subfield code="9">90-247-3562-9</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)632600138</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV009226699</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">und</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-29T</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4952</subfield><subfield code="0">(DE-625)157425:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Design systems for VLSI circuits</subfield><subfield code="b">logic synthesis and silicon compilation ; [proceedings of the NATO Advanced Study Inst. on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7 - 18, 1986]</subfield><subfield code="c">ed. by G. De Micheli</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Dordrecht u.a.</subfield><subfield code="b">Nijhoff</subfield><subfield code="c">1987</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">VIII, 651 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">NATO: NATO ASI series / E</subfield><subfield code="v">136</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Mathematische Methode</subfield><subfield code="0">(DE-588)4155620-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="y">1986</subfield><subfield code="z">L'Aquila</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="3" ind2="0"><subfield code="a">Mathematische Methode</subfield><subfield code="0">(DE-588)4155620-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2=" "><subfield code="8">3\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">De Micheli, Giovanni</subfield><subfield code="d">1955-</subfield><subfield code="e">Sonstige</subfield><subfield code="0">(DE-588)114063575</subfield><subfield code="4">oth</subfield></datafield><datafield tag="711" ind1="2" ind2=" "><subfield code="a">Advanced Study Institute on Logic Synthesis and Silicon Compilation for VLSI Design</subfield><subfield code="d">1986</subfield><subfield code="c">L'Aquila</subfield><subfield code="j">Sonstige</subfield><subfield code="0">(DE-588)806439-8</subfield><subfield code="4">oth</subfield></datafield><datafield tag="810" ind1="2" ind2=" "><subfield code="a">E</subfield><subfield code="t">NATO: NATO ASI series</subfield><subfield code="v">136</subfield><subfield code="w">(DE-604)BV000007015</subfield><subfield code="9">136</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">3\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-006135487</subfield></datafield></record></collection> |
genre | (DE-588)1071861417 Konferenzschrift 1986 L'Aquila gnd-content |
genre_facet | Konferenzschrift 1986 L'Aquila |
id | DE-604.BV009226699 |
illustrated | Not Illustrated |
indexdate | 2025-01-10T13:18:10Z |
institution | BVB |
institution_GND | (DE-588)806439-8 |
isbn | 9024735610 9024735629 |
language | Undetermined |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006135487 |
oclc_num | 632600138 |
open_access_boolean | |
owner | DE-29T |
owner_facet | DE-29T |
physical | VIII, 651 S. |
publishDate | 1987 |
publishDateSearch | 1987 |
publishDateSort | 1987 |
publisher | Nijhoff |
record_format | marc |
series2 | NATO: NATO ASI series / E |
spelling | Design systems for VLSI circuits logic synthesis and silicon compilation ; [proceedings of the NATO Advanced Study Inst. on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7 - 18, 1986] ed. by G. De Micheli Dordrecht u.a. Nijhoff 1987 VIII, 651 S. txt rdacontent n rdamedia nc rdacarrier NATO: NATO ASI series / E 136 Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Mathematische Methode (DE-588)4155620-3 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1986 L'Aquila gnd-content VLSI (DE-588)4117388-0 s Logischer Entwurf (DE-588)4168051-0 s DE-604 Entwurf (DE-588)4121208-3 s 1\p DE-604 Schaltungsentwurf (DE-588)4179389-4 s 2\p DE-604 Mathematische Methode (DE-588)4155620-3 s 3\p DE-604 De Micheli, Giovanni 1955- Sonstige (DE-588)114063575 oth Advanced Study Institute on Logic Synthesis and Silicon Compilation for VLSI Design 1986 L'Aquila Sonstige (DE-588)806439-8 oth E NATO: NATO ASI series 136 (DE-604)BV000007015 136 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Design systems for VLSI circuits logic synthesis and silicon compilation ; [proceedings of the NATO Advanced Study Inst. on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7 - 18, 1986] Schaltungsentwurf (DE-588)4179389-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd Mathematische Methode (DE-588)4155620-3 gnd Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
subject_GND | (DE-588)4179389-4 (DE-588)4168051-0 (DE-588)4155620-3 (DE-588)4121208-3 (DE-588)4117388-0 (DE-588)1071861417 |
title | Design systems for VLSI circuits logic synthesis and silicon compilation ; [proceedings of the NATO Advanced Study Inst. on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7 - 18, 1986] |
title_auth | Design systems for VLSI circuits logic synthesis and silicon compilation ; [proceedings of the NATO Advanced Study Inst. on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7 - 18, 1986] |
title_exact_search | Design systems for VLSI circuits logic synthesis and silicon compilation ; [proceedings of the NATO Advanced Study Inst. on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7 - 18, 1986] |
title_full | Design systems for VLSI circuits logic synthesis and silicon compilation ; [proceedings of the NATO Advanced Study Inst. on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7 - 18, 1986] ed. by G. De Micheli |
title_fullStr | Design systems for VLSI circuits logic synthesis and silicon compilation ; [proceedings of the NATO Advanced Study Inst. on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7 - 18, 1986] ed. by G. De Micheli |
title_full_unstemmed | Design systems for VLSI circuits logic synthesis and silicon compilation ; [proceedings of the NATO Advanced Study Inst. on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7 - 18, 1986] ed. by G. De Micheli |
title_short | Design systems for VLSI circuits |
title_sort | design systems for vlsi circuits logic synthesis and silicon compilation proceedings of the nato advanced study inst on logic synthesis and silicon compilation for vlsi design l aquila italy july 7 18 1986 |
title_sub | logic synthesis and silicon compilation ; [proceedings of the NATO Advanced Study Inst. on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7 - 18, 1986] |
topic | Schaltungsentwurf (DE-588)4179389-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd Mathematische Methode (DE-588)4155620-3 gnd Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
topic_facet | Schaltungsentwurf Logischer Entwurf Mathematische Methode Entwurf VLSI Konferenzschrift 1986 L'Aquila |
volume_link | (DE-604)BV000007015 |
work_keys_str_mv | AT demicheligiovanni designsystemsforvlsicircuitslogicsynthesisandsiliconcompilationproceedingsofthenatoadvancedstudyinstonlogicsynthesisandsiliconcompilationforvlsidesignlaquilaitalyjuly7181986 AT advancedstudyinstituteonlogicsynthesisandsiliconcompilationforvlsidesignlaquila designsystemsforvlsicircuitslogicsynthesisandsiliconcompilationproceedingsofthenatoadvancedstudyinstonlogicsynthesisandsiliconcompilationforvlsidesignlaquilaitalyjuly7181986 |