An improved write buffer design for a write-through cache:
Abstract: "A write buffer is a device to reduce processor stalls when there are consecutive writes from CPU to main memory. Buffering is required for a cache in either write-back mode or write-through mode, but it is more important in the write-through mode because of a higher write frequency....
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Urbana, Ill.
1991
|
| Schriftenreihe: | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report
1105 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "A write buffer is a device to reduce processor stalls when there are consecutive writes from CPU to main memory. Buffering is required for a cache in either write-back mode or write-through mode, but it is more important in the write-through mode because of a higher write frequency. A write buffer of capacity four was thought to provide most of the performance improvement possible in a write-through cache. In this paper, a trace-driven simulation on the SPARC machine is used to re- evaluate write buffer performance, including the read conflict effect. Results show that the read conflicts do not produce a serious degradation, but write stalls are still frequent when a slow main memory is used, no matter what the capacity of the buffer is Two improved write buffer designs are studied: the write-merging strategy, merging writes to the same (line) address into one in the buffer, and the write-back write buffer, reducing write traffic as in a write-back cache. The results show that both designs are effective in improving the performance without excessive costs. The write-back write buffer has a better performance, but the write buffer using write-merging can still maintain the write-through policy. |
| Beschreibung: | 18 S. |
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| 100 | 1 | |a Chen, Yung-Chin |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a An improved write buffer design for a write-through cache |c Yung-Chin Chen and Alexander V. Veidenbaum |
| 264 | 1 | |a Urbana, Ill. |c 1991 | |
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| 490 | 1 | |a Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |v 1105 | |
| 520 | 3 | |a Abstract: "A write buffer is a device to reduce processor stalls when there are consecutive writes from CPU to main memory. Buffering is required for a cache in either write-back mode or write-through mode, but it is more important in the write-through mode because of a higher write frequency. A write buffer of capacity four was thought to provide most of the performance improvement possible in a write-through cache. In this paper, a trace-driven simulation on the SPARC machine is used to re- evaluate write buffer performance, including the read conflict effect. Results show that the read conflicts do not produce a serious degradation, but write stalls are still frequent when a slow main memory is used, no matter what the capacity of the buffer is | |
| 520 | 3 | |a Two improved write buffer designs are studied: the write-merging strategy, merging writes to the same (line) address into one in the buffer, and the write-back write buffer, reducing write traffic as in a write-back cache. The results show that both designs are effective in improving the performance without excessive costs. The write-back write buffer has a better performance, but the write buffer using write-merging can still maintain the write-through policy. | |
| 650 | 4 | |a Cache memory | |
| 700 | 1 | |a Veidenbaum, Alexander V. |e Verfasser |4 aut | |
| 830 | 0 | |a Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |v 1105 |w (DE-604)BV008930033 |9 1105 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-006133932 | ||
Datensatz im Suchindex
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| any_adam_object | |
| author | Chen, Yung-Chin Veidenbaum, Alexander V. |
| author_facet | Chen, Yung-Chin Veidenbaum, Alexander V. |
| author_role | aut aut |
| author_sort | Chen, Yung-Chin |
| author_variant | y c c ycc a v v av avv |
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| bvnumber | BV009224759 |
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| id | DE-604.BV009224759 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:33:25Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006133932 |
| oclc_num | 26513231 |
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| physical | 18 S. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| record_format | marc |
| series | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |
| series2 | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |
| spelling | Chen, Yung-Chin Verfasser aut An improved write buffer design for a write-through cache Yung-Chin Chen and Alexander V. Veidenbaum Urbana, Ill. 1991 18 S. txt rdacontent n rdamedia nc rdacarrier Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report 1105 Abstract: "A write buffer is a device to reduce processor stalls when there are consecutive writes from CPU to main memory. Buffering is required for a cache in either write-back mode or write-through mode, but it is more important in the write-through mode because of a higher write frequency. A write buffer of capacity four was thought to provide most of the performance improvement possible in a write-through cache. In this paper, a trace-driven simulation on the SPARC machine is used to re- evaluate write buffer performance, including the read conflict effect. Results show that the read conflicts do not produce a serious degradation, but write stalls are still frequent when a slow main memory is used, no matter what the capacity of the buffer is Two improved write buffer designs are studied: the write-merging strategy, merging writes to the same (line) address into one in the buffer, and the write-back write buffer, reducing write traffic as in a write-back cache. The results show that both designs are effective in improving the performance without excessive costs. The write-back write buffer has a better performance, but the write buffer using write-merging can still maintain the write-through policy. Cache memory Veidenbaum, Alexander V. Verfasser aut Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report 1105 (DE-604)BV008930033 1105 |
| spellingShingle | Chen, Yung-Chin Veidenbaum, Alexander V. An improved write buffer design for a write-through cache Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report Cache memory |
| title | An improved write buffer design for a write-through cache |
| title_auth | An improved write buffer design for a write-through cache |
| title_exact_search | An improved write buffer design for a write-through cache |
| title_full | An improved write buffer design for a write-through cache Yung-Chin Chen and Alexander V. Veidenbaum |
| title_fullStr | An improved write buffer design for a write-through cache Yung-Chin Chen and Alexander V. Veidenbaum |
| title_full_unstemmed | An improved write buffer design for a write-through cache Yung-Chin Chen and Alexander V. Veidenbaum |
| title_short | An improved write buffer design for a write-through cache |
| title_sort | an improved write buffer design for a write through cache |
| topic | Cache memory |
| topic_facet | Cache memory |
| volume_link | (DE-604)BV008930033 |
| work_keys_str_mv | AT chenyungchin animprovedwritebufferdesignforawritethroughcache AT veidenbaumalexanderv animprovedwritebufferdesignforawritethroughcache |