Combining hardware and software cache coherence strategies:
Abstract: "Efficiently maintaining cache coherence is a major problem in large-scale shared memory multiprocessors. Hardware directory schemes have very high memory requirements, while software-directed schemes must rely on imprecise compile-time memory disambiguation. Recently proposed dynamic...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Urbana, Ill.
1991
|
| Schriftenreihe: | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report
1057 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "Efficiently maintaining cache coherence is a major problem in large-scale shared memory multiprocessors. Hardware directory schemes have very high memory requirements, while software-directed schemes must rely on imprecise compile-time memory disambiguation. Recently proposed dynamic directory schemes allocate pointers to blocks only as they are referenced, which significantly reduces their memory requirements, but they still allocate pointers to blocks that do not need them. We show how compiler marking can further reduce the directory size by allocating pointers only when necessary. Using trace-driven simulations, we find that the performance of this new approach is comparable to other coherence schemes, but with significantly lower memory requirements." |
| Beschreibung: | 11 S. |
Internformat
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| 100 | 1 | |a Lilja, David J. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Combining hardware and software cache coherence strategies |c David J. Lilja and Pen-Chung Yew |
| 264 | 1 | |a Urbana, Ill. |c 1991 | |
| 300 | |a 11 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |v 1057 | |
| 520 | 3 | |a Abstract: "Efficiently maintaining cache coherence is a major problem in large-scale shared memory multiprocessors. Hardware directory schemes have very high memory requirements, while software-directed schemes must rely on imprecise compile-time memory disambiguation. Recently proposed dynamic directory schemes allocate pointers to blocks only as they are referenced, which significantly reduces their memory requirements, but they still allocate pointers to blocks that do not need them. We show how compiler marking can further reduce the directory size by allocating pointers only when necessary. Using trace-driven simulations, we find that the performance of this new approach is comparable to other coherence schemes, but with significantly lower memory requirements." | |
| 650 | 4 | |a Cache memory | |
| 650 | 4 | |a Compilers (Computer programs) | |
| 650 | 4 | |a Multiprocessors | |
| 700 | 1 | |a Yew, Pen-Chung |e Verfasser |4 aut | |
| 830 | 0 | |a Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |v 1057 |w (DE-604)BV008930033 |9 1057 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-006133919 | ||
Datensatz im Suchindex
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| any_adam_object | |
| author | Lilja, David J. Yew, Pen-Chung |
| author_facet | Lilja, David J. Yew, Pen-Chung |
| author_role | aut aut |
| author_sort | Lilja, David J. |
| author_variant | d j l dj djl p c y pcy |
| building | Verbundindex |
| bvnumber | BV009224746 |
| ctrlnum | (OCoLC)24892666 (DE-599)BVBBV009224746 |
| format | Book |
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| id | DE-604.BV009224746 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:33:25Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006133919 |
| oclc_num | 24892666 |
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| owner_facet | DE-29T |
| physical | 11 S. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| record_format | marc |
| series | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |
| series2 | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |
| spelling | Lilja, David J. Verfasser aut Combining hardware and software cache coherence strategies David J. Lilja and Pen-Chung Yew Urbana, Ill. 1991 11 S. txt rdacontent n rdamedia nc rdacarrier Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report 1057 Abstract: "Efficiently maintaining cache coherence is a major problem in large-scale shared memory multiprocessors. Hardware directory schemes have very high memory requirements, while software-directed schemes must rely on imprecise compile-time memory disambiguation. Recently proposed dynamic directory schemes allocate pointers to blocks only as they are referenced, which significantly reduces their memory requirements, but they still allocate pointers to blocks that do not need them. We show how compiler marking can further reduce the directory size by allocating pointers only when necessary. Using trace-driven simulations, we find that the performance of this new approach is comparable to other coherence schemes, but with significantly lower memory requirements." Cache memory Compilers (Computer programs) Multiprocessors Yew, Pen-Chung Verfasser aut Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report 1057 (DE-604)BV008930033 1057 |
| spellingShingle | Lilja, David J. Yew, Pen-Chung Combining hardware and software cache coherence strategies Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report Cache memory Compilers (Computer programs) Multiprocessors |
| title | Combining hardware and software cache coherence strategies |
| title_auth | Combining hardware and software cache coherence strategies |
| title_exact_search | Combining hardware and software cache coherence strategies |
| title_full | Combining hardware and software cache coherence strategies David J. Lilja and Pen-Chung Yew |
| title_fullStr | Combining hardware and software cache coherence strategies David J. Lilja and Pen-Chung Yew |
| title_full_unstemmed | Combining hardware and software cache coherence strategies David J. Lilja and Pen-Chung Yew |
| title_short | Combining hardware and software cache coherence strategies |
| title_sort | combining hardware and software cache coherence strategies |
| topic | Cache memory Compilers (Computer programs) Multiprocessors |
| topic_facet | Cache memory Compilers (Computer programs) Multiprocessors |
| volume_link | (DE-604)BV008930033 |
| work_keys_str_mv | AT liljadavidj combininghardwareandsoftwarecachecoherencestrategies AT yewpenchung combininghardwareandsoftwarecachecoherencestrategies |