CAD geometry data exchange using STEP: realisation of interface processors
Gespeichert in:
| Format: | Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
Springer
1993
|
| Schriftenreihe: | Research reports ESPRIT
2195 : PDT ; 1 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Literaturverz. S. 430 - 432 |
| Beschreibung: | XIV, 432 S. Ill., graph. Darst. |
| ISBN: | 3540569022 0387569022 |
Internformat
MARC
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| 245 | 1 | 0 | |a CAD geometry data exchange using STEP |b realisation of interface processors |c H. J. Helpenstein (ed.) |
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 1993 | |
| 300 | |a XIV, 432 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Research reports ESPRIT : 2195 : PDT |v 1 | |
| 500 | |a Literaturverz. S. 430 - 432 | ||
| 630 | 0 | 7 | |a STEP |g Norm |0 (DE-588)4332027-2 |2 gnd |9 rswk-swf |
| 650 | 4 | |a Computer-aided design | |
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| 700 | 1 | |a Helpenstein, Helmut J. |e Sonstige |4 oth | |
| 830 | 0 | |a Research reports ESPRIT |v 2195 : PDT ; 1 |w (DE-604)BV009110296 |9 1 | |
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| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-006040580 | |
Datensatz im Suchindex
| _version_ | 1822490804191494144 |
|---|---|
| adam_text |
TABLE
OF
CONTENTS
1.
INTRODUCTION
.
1
2.
APPLICATION
PROTOCOLS
AND
STEP
RELATIONS
.
3
2.1
ENTITY
TABLES
AND
MAPPING
TO
STEP
.
3
2.1.1
OBJECTIVES
FOR
THE
TABLE
OF
ENTITIES
.
3
2.1.2
THE
TABLE
OF
NATIVE
ENTITIES
MAPPED
TO
STEP
.
4
2.1.3
OTHER
CAD
MODEL
ENTITIES
WHICH
REQUIRE
A
STEP
MODEL
TRANSFER
.
7
2.1.4
A
GENERAL
ASSOCIATION
CAPABILITY
.
9
2.1.5
CONSIDERATIONS
ON
THE
ATTRIBUTE
ASSOCIATION
OF
STEP
ENTITIES.
11
2.2
WORK
IN
THE
ISO
AND
THE
CONCEPT
OF
APPLICATION
PROTOCOLS.
15
2.2.1
OVERVIEW
ON
CADEX
CONTRIBUTIONS
AND
ACTIVITIES
TO
ISO/STEP
.
15
2.2.2
THE
CONCEPT
OF
AN
APPLICATION
PROTOCOL
.
17
2.2.3
TABLE
OF
CONTENTS
OF
AN
ISO
APPLICATION
PROTOCOL.
22
2.2.4
THE
MECHANICAL
DESIGN
APPLICATION
PROTOCOL
CONCEPT
.
24
2.2.5
LIST
OF
OPEN
STEP
ISSUES
FROM
CADEX
POINT
OF
VIEW.
26
2.2.6
RECOMMENDATIONS
TO
STEP
.
27
2.2.7
OTHER
ISO
WORK
.
30
2.3
ISO
APPLICATION
PROTOCOLS
.
31
2.3.1
APPLICATION
PROTOCOL
FOR
MECHANICAL
DESIGN
USING
BOUNDARY
REPRESENTATION
.
31
2.3.2
APPLICATION
PROTOCOL
FOR
MECHANICAL
DESIGN
USING
SURFACE
REPRESENTATION
.
35
2.3.3
APPLICATION
PROTOCOL
FOR
MECHANICAL
DESIGN
USING
WIREFAME
REPRESENTATION
.
38
X
TABLE
OF
CONTENTS
2.3.4
EXPRESS
LONG
FORM
OF
THE
PRODUCT
STRUCTURE
MODULE
.
40
2.4
OTHER
CADEX
APPLICATION
PROTOCOLS.
46
2.5
RELATIONSHIPS
BETWEEN
APPLICATION
PROTOCOLS
.
47
2.5.1
DOMAINS
OF
THE
APPLICATION
PROTOCOLS
.
47
2.5.2 CONVERSION
BETWEEN
DIFFERENT
APPLICATION
PROTOCOLS
.
5
1
2.5.3
SHAPE
ENTITES
FROM
MULTIPLE
APS
IN
SINGLE
FILES
.
53
2.5.4
APPLICATION
INTERPRETED
CONSTRUCTS
.
55
3.
COMMON
TOOL
KIT
.
58
3.1
INTRODUCTION
.
58
3.2
THE
ARCHITECTURE
OF
THE
CADEX
PRE
AND
POSTPROCESSORS
.
59
3.2.1
OVERVIEW
.
59
3.2.2
DESCRIPTION
OF
THE
ARCHITECTURE.
60
3.2.3
ORGANISATION
OF
THE
DEVELOPMENT
.
62
3.3
TECHNICAL
DESCRIPTION
.
62
3.3.1
IDS
.
62
3.3.2
SCANNER
AND
PARSER
.
67
3.3.3
FORMATTER
.
93
3.3.4
CHECKER
.
99
3.3.5
STATISTICS
TOOLS
.
104
3.3.6 CONVERSION
TOOLS
.
112
3.3.6.1
GENERAL
REMARKS
ON
CONVERSION
TOOLS
.
112
3.3.6.2
CONVERSION
TOOLS
BY
SI
.
115
3.3.6.3
CONVERSION
TOOLS
BY
GFS
.
170
3.3.6.4
CONVERSION
TOOLS
BY
FEGS
LTD
.
204
3.4
USER'S
GUIDE
.
226
3.4.1
IDS
.
226
3.4.2
SCANNER
AND
PARSER
.
228
3.4.3
FORMATTER
.
232
3.4.4
CHECKER
.
237
3.4.5
STATISTICS
TOOLS
.
242
3.4.6
USER'S
GUIDE
OF
SI
TOOLS
.
253
3.4.7
USER'S
GUIDE
OF
GFS
TOOLS
.
266
3.4.8
USER'S
GUIDE
OF
FEGS
TOOLS
.
274
TABLE
OF
CONTENTS
XI
4.
DEVELOPMENT
OF
PROCESSORS
.
280
4.1
DET
NORSKE
VERITAS
RESEARCH
.
280
4.1.1
INTRODUCTION
.
280
4.1.2
PROCESSOR
ARCHITECTURE
.
281
4.1.3
POST-PROCESSOR
BACKEND
.
281
4.1.4
POST-PROCESSOR
CONVERSION
.
282
4.1.5
PRE-PROCESSOR
FRONTEND.
282
4.1.6
AVAILABLE
PROCESSORS
.
283
4.1.7
FUTURE
.
283
4.1.8
EXAMPLES
.
284
4.2
DISEL
.
284
4.2.1
INTRODUCTION
.
284
4.2.2
DEVELOPMENT
ENVIRONMENT
.
285
4.2.3
PROCESSORS
DESCRIPTION
.
286
4.3
FEGSLTD
.
291
4.3.1
INTRODUCTION
.
291
4.3.2
THE
STATUS
OF
FAM
.
292
4.3.3
THE
PROCESSORS
THAT
HAVE
BEEN
DEVELOPED
.
293
4.3.4
REQUIREMENTS
TO
THE
PROCESSORS
.
294
4.3.5
SYSTEM
ARCHITECTURE
.
294
4.3.6
USER
INTERFACE
AND
SOFTWARE
OPERATION
.
295
4.3.7
TRANSFER
BETWEEN
IDS
AND
FAM
.
296
4.3.8
CONVERSIONS
BETWEEN
IDS
AND
FAM
.
296
4.3.9
CONVERSIONS
BETWEEN
STEP
ENTITIES
ON
IDS
.
298
4.3.10
THE
SUPPORT
OF
THE
BOUNDARY-REPRESENTATION
AP,
ISO
10303-204.299
4.3.11
THE
SUPPORT
OF
THE
SURFACE
AP,
ISO
10303-205
.
300
4.3.12
THE
SUPPORT
OF
THE
WIRE
FRAME
AP,
ISO
10303-206
.
300
4.3.13
THE
SUPPORT
OF
THE
COMPOUND
B-REP
AP.
.
301
4.3.14
CURRENT
STATUS
.
301
4.3.15
THE
EXPERIENCE
GAINED
IN
THE
PROJECT
.
302
4.3.16
FUTURE
PLANS,
FAM
AND
FAMEXCHANGE
.
302
4.4
GESELLSCHAFT
FILR
STRUKTURANALYSE
.
303
4.4.1
INTRODUCTION
.
303
4.4.2
MODELS
TO
BE
COVERED.
304
4.4.3
FUNCTIONALITY
.
305
4.4.4
IMPLEMENTATION
AND
TEST
.
306
XII
TABLE
OF
CONTENTS
4.5
HEWLETT-PACKARD
.
308
4.5.1
INTRODUCTION
.
308
4.5.2
HP'S
ME30
STEP
PRE-PROCESSOR
.
308
4.5.3
HP'S
SOLIDDESIGNER
STEP
POST-PROCESSOR
.
314
4.5.4
HP'S
SOLIDDESIGNER
STEP
PRE-PROCESSOR
.
320
4.5.5
EXAMPLES
OF
MODEL
EXCHANGE
.
322
4.5.6
REFERENCES
.
323
4.6
ISYKON
AND
PROCAD
.
324
4.6.1
INTRODUCTION
.
324
4.6.2
THE
PRE-PROCESSORS
.
324
4.6.3
THE
POST-PROCESSORS
.
327
4.6.4
THE
DIALOGUE
LANGUAGE
.
330
4.6.5
INTEGRATED
TEST
TOOLS
.
332
4.6.6
SUMMARY
.
332
4.7
ITALCAD
.
333
4.7.1
INTRODUCTION
.
333
4.7.2
PROCESSOR
ARCHITECTURE
.
333
4.7.3
PROCESSORS
BUILT
.
335
4.7.4
IMPLEMENTATION
AND
TEST
.
337
4.8 KONGSBERG
3D
PARTNER
A.S
.
337
4.8.1
INTRODUCTION
.
337
4.8.2
SYSTEM
ARCHITECTURE
.
338
4.8.3
PRE-PROCESSOR
IMPLEMENTATION
.
339
4.8.4
POST-PROCESSOR
IMPLEMENTATION
.
340
4.8.5
ERROR
AND
LOG
HANDLING
.
343
4.8.6
TESTING
.
345
4.8.8
COMMENTS
AND
EXPLOITATION
OF
RESULTS.
348
4.9
SENTER
FOR
INDUSTRIFORSKNING.
348
4.9.1
SUMMARY
AND
APPLICABLE
DOCUMENTS
.
348
4.9.2
THE
SISL
SYSTEM
.
349
4.9.3
REQUIREMENTS
FOR
THE
SISL-STEP
INTERFACE
.
351
4.9.4
ARCHITECTURE
OF
THE
SISL-STEP
PROCESSORS.
352
4.9.5
GENERAL
INFORMATION
ON
THE
SISL-STEP
PROCESSORS
.
355
4.9.6
PROCESSOR
DETAILS
.
361
TABLE
OF
CONTENTS
XIII
4.10
SIEMENS-NIXDORF-INFORMATIONSSYSTEME
.
365
4.10.1
OVERVIEW
.
365
4.10.2
SYSTEM
AND
PROCESSOR
ARCHITECTURE.
365
4.10.3
PROCESSOR
FOR
SF-AP
.
368
4.10.4
PROCESSOR
FOR
BREP-AP
.
373
5.
TEST
AND
VALIDATION.
378
5.1
INTRODUCTION
.
378
5.2
USER
ACCEPTANCE
TESTING
.
379
5.2.1
THE
USER
ROLES
IN
CADEX
.
379
5.2.2
TYPES
OF
TESTS
.
380
5.2.3
TEST
DATA
.
380
5.2.4
TEST
PROCEDURES
.
384
5.2.5
SOFTWARE
TOOL
SUPPORT
.
384
5.3
CONFORMANCE
TESTING
.
385
5.3.1
INTRODUCTION
AND
DEFINITION
.
385
5.3.2
MOTIVATION
FOR
PERFORMING
CONFORMANCE
TESTING.
.
385
5.3.3
INFLUENCE
OF
THE
CEC
FUNDED
CTS2
PROJECT
.
385
5.3.4 TYPES
OF
TESTS
.
386
5.3.5
AP
CONFORMANCE
REQUIREMENTS
.
386
5.3.6
AP
TEST
PURPOSES
.
394
5.3.7
TEST
DATA
AND
PROCEDURES
.
397
5.4
THE
FIAT
TEST
LIBRARY
.
398
5.4.1
CHOICE
OF
THE
MODELS
.
398
5.4.2
MODEL
GENERATION
DESCRIPTION
(MGD)
.
403
5.4.3
DATA
TRANSFER
EVALUATION
CRITERIA.
.
407
5.5
TEST
PLAN
AND
RESULTS
.
408
5.5.1
TEST
PLAN
.
408
5.5.2
TEST
RESULTS
OF
GESELLSCHAFT
FTLR
STRUKTURANALYSE.
.
413
5.5.3
TEST
RESULTS
OF
SIEMENS
NIXDORF.
.
419
5.5.4
TEST
RESULTS
OF
SENTER
FOR
INDUSTRIFORSKNING
.
420
5.5.5
TEST
RESULTS
OF
KONGSBERG
3D
PARTNER
A.S
.
422
5.5.6
TEST
RESULTS
OF
ITALCAD
.
424
5.5.7
TEST
RESULTS
OF
PROCAD
AND
ISYKON
.
424
XIV
TABLE
OF
CONTENTS
5.5.8
TEST
RESULTS
OF
HEWLETT
PACKARD
.
426
5.5.9
TEST
RESULTS
OF
DISEL
.
429
5.6
BIBLIOGRAPHY
.
430 |
| any_adam_object | 1 |
| building | Verbundindex |
| bvnumber | BV009110351 |
| callnumber-first | T - Technology |
| callnumber-label | TA174 |
| callnumber-raw | TA174 |
| callnumber-search | TA174 |
| callnumber-sort | TA 3174 |
| callnumber-subject | TA - General and Civil Engineering |
| classification_tum | DAT 810f DAT 252f |
| ctrlnum | (OCoLC)635619273 (DE-599)BVBBV009110351 |
| dewey-full | 620/.0042/0285 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 620 - Engineering and allied operations |
| dewey-raw | 620/.0042/0285 |
| dewey-search | 620/.0042/0285 |
| dewey-sort | 3620 242 3285 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik |
| format | Book |
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| id | DE-604.BV009110351 |
| illustrated | Illustrated |
| indexdate | 2025-01-28T11:11:11Z |
| institution | BVB |
| isbn | 3540569022 0387569022 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006040580 |
| oclc_num | 635619273 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-19 DE-BY-UBM DE-634 DE-83 DE-188 |
| owner_facet | DE-91G DE-BY-TUM DE-19 DE-BY-UBM DE-634 DE-83 DE-188 |
| physical | XIV, 432 S. Ill., graph. Darst. |
| publishDate | 1993 |
| publishDateSearch | 1993 |
| publishDateSort | 1993 |
| publisher | Springer |
| record_format | marc |
| series | Research reports ESPRIT |
| series2 | Research reports ESPRIT : 2195 : PDT |
| spelling | CAD geometry data exchange using STEP realisation of interface processors H. J. Helpenstein (ed.) Berlin [u.a.] Springer 1993 XIV, 432 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Research reports ESPRIT : 2195 : PDT 1 Literaturverz. S. 430 - 432 STEP Norm (DE-588)4332027-2 gnd rswk-swf Computer-aided design Microprocessors Datenaustausch (DE-588)4227289-0 gnd rswk-swf Prozessor (DE-588)4176076-1 gnd rswk-swf Programmierumgebung (DE-588)4134837-0 gnd rswk-swf Abnahme (DE-588)4141076-2 gnd rswk-swf Test (DE-588)4059549-3 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf Produktdaten (DE-588)4298695-3 gnd rswk-swf ISO-Norm (DE-588)4282630-5 gnd rswk-swf Kommunikationsprotokoll (DE-588)4128252-8 gnd rswk-swf CAD (DE-588)4069794-0 s Produktdaten (DE-588)4298695-3 s STEP Norm (DE-588)4332027-2 u DE-604 Test (DE-588)4059549-3 s 1\p DE-604 Programmierumgebung (DE-588)4134837-0 s 2\p DE-604 Prozessor (DE-588)4176076-1 s 3\p DE-604 Datenaustausch (DE-588)4227289-0 s 4\p DE-604 ISO-Norm (DE-588)4282630-5 s 5\p DE-604 Abnahme (DE-588)4141076-2 s 6\p DE-604 Kommunikationsprotokoll (DE-588)4128252-8 s 7\p DE-604 Helpenstein, Helmut J. Sonstige oth Research reports ESPRIT 2195 : PDT ; 1 (DE-604)BV009110296 1 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006040580&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 5\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 6\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 7\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | CAD geometry data exchange using STEP realisation of interface processors Research reports ESPRIT STEP Norm (DE-588)4332027-2 gnd Computer-aided design Microprocessors Datenaustausch (DE-588)4227289-0 gnd Prozessor (DE-588)4176076-1 gnd Programmierumgebung (DE-588)4134837-0 gnd Abnahme (DE-588)4141076-2 gnd Test (DE-588)4059549-3 gnd CAD (DE-588)4069794-0 gnd Produktdaten (DE-588)4298695-3 gnd ISO-Norm (DE-588)4282630-5 gnd Kommunikationsprotokoll (DE-588)4128252-8 gnd |
| subject_GND | (DE-588)4332027-2 (DE-588)4227289-0 (DE-588)4176076-1 (DE-588)4134837-0 (DE-588)4141076-2 (DE-588)4059549-3 (DE-588)4069794-0 (DE-588)4298695-3 (DE-588)4282630-5 (DE-588)4128252-8 |
| title | CAD geometry data exchange using STEP realisation of interface processors |
| title_auth | CAD geometry data exchange using STEP realisation of interface processors |
| title_exact_search | CAD geometry data exchange using STEP realisation of interface processors |
| title_full | CAD geometry data exchange using STEP realisation of interface processors H. J. Helpenstein (ed.) |
| title_fullStr | CAD geometry data exchange using STEP realisation of interface processors H. J. Helpenstein (ed.) |
| title_full_unstemmed | CAD geometry data exchange using STEP realisation of interface processors H. J. Helpenstein (ed.) |
| title_short | CAD geometry data exchange using STEP |
| title_sort | cad geometry data exchange using step realisation of interface processors |
| title_sub | realisation of interface processors |
| topic | STEP Norm (DE-588)4332027-2 gnd Computer-aided design Microprocessors Datenaustausch (DE-588)4227289-0 gnd Prozessor (DE-588)4176076-1 gnd Programmierumgebung (DE-588)4134837-0 gnd Abnahme (DE-588)4141076-2 gnd Test (DE-588)4059549-3 gnd CAD (DE-588)4069794-0 gnd Produktdaten (DE-588)4298695-3 gnd ISO-Norm (DE-588)4282630-5 gnd Kommunikationsprotokoll (DE-588)4128252-8 gnd |
| topic_facet | STEP Norm Computer-aided design Microprocessors Datenaustausch Prozessor Programmierumgebung Abnahme Test CAD Produktdaten ISO-Norm Kommunikationsprotokoll |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006040580&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV009110296 |
| work_keys_str_mv | AT helpensteinhelmutj cadgeometrydataexchangeusingsteprealisationofinterfaceprocessors |