Systolic algorithms for the CMU warp processor:
Abstract: "CMU is building a 32-bit floating-point systolic array that can efficiently perform many essential computations in signal processing like the FFT and convolution. This is a one-dimensional systolic array that in general takes inputs from one end cell and produces outputs at the other...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Pittsburgh, Pa.
1984
|
| Ausgabe: | Rev. |
| Schriftenreihe: | Carnegie-Mellon University <Pittsburgh, Pa.> / Computer Science Department: CMU-CS
84,158 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "CMU is building a 32-bit floating-point systolic array that can efficiently perform many essential computations in signal processing like the FFT and convolution. This is a one-dimensional systolic array that in general takes inputs from one end cell and produces outputs at the other end, with data and control all flowing in one direction. We call this particular systolic array the Warp processor, suggesting that it can perform various transformations at a very high speed. We expect to have wide applications for the Warp processor, especially for the CMU prototype which has high degrees of flexibility at the expense of a relatively high chip count for each cell The prototype has 10 cells, each of which is capable of performing 10 million floating-point operations per second (10 MFLOPS) and is build on a single board using only off-the-shelf components. This 10-cell processor for example can process 1024-point complex FFTs at a rate of one FFT every 600 [mu]s. Under program control, the same processor can perform many other primitive computations in signal, image and vision processing, including two-dimensional convolution and complex matrix multiplication, at a rate of 100 MFLOPS. Together with another processor capable of performing divisions and square roots, the processor can also efficiently carry out a number of difficult matrix operations such as solving covariant linear systems, a crucial computation in real-time adaptive signal processing. This paper outlines the architecture of the Warp processor and describes how the signal processing tasks are implemented on the processor. |
| Beschreibung: | 20 S. |
Internformat
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| 245 | 1 | 0 | |a Systolic algorithms for the CMU warp processor |
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| 490 | 1 | |a Carnegie-Mellon University <Pittsburgh, Pa.> / Computer Science Department: CMU-CS |v 84,158 | |
| 520 | 3 | |a Abstract: "CMU is building a 32-bit floating-point systolic array that can efficiently perform many essential computations in signal processing like the FFT and convolution. This is a one-dimensional systolic array that in general takes inputs from one end cell and produces outputs at the other end, with data and control all flowing in one direction. We call this particular systolic array the Warp processor, suggesting that it can perform various transformations at a very high speed. We expect to have wide applications for the Warp processor, especially for the CMU prototype which has high degrees of flexibility at the expense of a relatively high chip count for each cell | |
| 520 | 3 | |a The prototype has 10 cells, each of which is capable of performing 10 million floating-point operations per second (10 MFLOPS) and is build on a single board using only off-the-shelf components. This 10-cell processor for example can process 1024-point complex FFTs at a rate of one FFT every 600 [mu]s. Under program control, the same processor can perform many other primitive computations in signal, image and vision processing, including two-dimensional convolution and complex matrix multiplication, at a rate of 100 MFLOPS. Together with another processor capable of performing divisions and square roots, the processor can also efficiently carry out a number of difficult matrix operations such as solving covariant linear systems, a crucial computation in real-time adaptive signal processing. This paper outlines the architecture of the Warp processor and describes how the signal processing tasks are implemented on the processor. | |
| 650 | 4 | |a Systolic array circuits | |
| 810 | 2 | |a Computer Science Department: CMU-CS |t Carnegie-Mellon University <Pittsburgh, Pa.> |v 84,158 |w (DE-604)BV006187264 |9 84,158 | |
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| dewey-tens | 620 - Engineering and allied operations |
| edition | Rev. |
| format | Book |
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| id | DE-604.BV009075571 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:30:35Z |
| institution | BVB |
| language | English |
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| physical | 20 S. |
| publishDate | 1984 |
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| series2 | Carnegie-Mellon University <Pittsburgh, Pa.> / Computer Science Department: CMU-CS |
| spelling | Kung, H. T. Verfasser aut Systolic algorithms for the CMU warp processor Rev. Pittsburgh, Pa. 1984 20 S. txt rdacontent n rdamedia nc rdacarrier Carnegie-Mellon University <Pittsburgh, Pa.> / Computer Science Department: CMU-CS 84,158 Abstract: "CMU is building a 32-bit floating-point systolic array that can efficiently perform many essential computations in signal processing like the FFT and convolution. This is a one-dimensional systolic array that in general takes inputs from one end cell and produces outputs at the other end, with data and control all flowing in one direction. We call this particular systolic array the Warp processor, suggesting that it can perform various transformations at a very high speed. We expect to have wide applications for the Warp processor, especially for the CMU prototype which has high degrees of flexibility at the expense of a relatively high chip count for each cell The prototype has 10 cells, each of which is capable of performing 10 million floating-point operations per second (10 MFLOPS) and is build on a single board using only off-the-shelf components. This 10-cell processor for example can process 1024-point complex FFTs at a rate of one FFT every 600 [mu]s. Under program control, the same processor can perform many other primitive computations in signal, image and vision processing, including two-dimensional convolution and complex matrix multiplication, at a rate of 100 MFLOPS. Together with another processor capable of performing divisions and square roots, the processor can also efficiently carry out a number of difficult matrix operations such as solving covariant linear systems, a crucial computation in real-time adaptive signal processing. This paper outlines the architecture of the Warp processor and describes how the signal processing tasks are implemented on the processor. Systolic array circuits Computer Science Department: CMU-CS Carnegie-Mellon University <Pittsburgh, Pa.> 84,158 (DE-604)BV006187264 84,158 |
| spellingShingle | Kung, H. T. Systolic algorithms for the CMU warp processor Systolic array circuits |
| title | Systolic algorithms for the CMU warp processor |
| title_auth | Systolic algorithms for the CMU warp processor |
| title_exact_search | Systolic algorithms for the CMU warp processor |
| title_full | Systolic algorithms for the CMU warp processor |
| title_fullStr | Systolic algorithms for the CMU warp processor |
| title_full_unstemmed | Systolic algorithms for the CMU warp processor |
| title_short | Systolic algorithms for the CMU warp processor |
| title_sort | systolic algorithms for the cmu warp processor |
| topic | Systolic array circuits |
| topic_facet | Systolic array circuits |
| volume_link | (DE-604)BV006187264 |
| work_keys_str_mv | AT kunght systolicalgorithmsforthecmuwarpprocessor |