Transistor sizing for timing optimization of combinational digital CMOS circuits:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Mikrofilm Buch |
| Sprache: | English |
| Veröffentlicht: |
1990
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| Schlagworte: | |
| Beschreibung: | Zürich, Techn. Hochsch., Diss.. - Mikroreprod. e. Ms. IX, 102 S. |
| Beschreibung: | 2 Mikrofiches 24x |
Internformat
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| 245 | 1 | 0 | |a Transistor sizing for timing optimization of combinational digital CMOS circuits |c by Lucas Sebastian Heusler |
| 264 | 1 | |c 1990 | |
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| 650 | 4 | |a Datenverarbeitung | |
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| 650 | 4 | |a Timing circuits |x Data processing | |
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Datensatz im Suchindex
| _version_ | 1804123365360795648 |
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| any_adam_object | |
| author | Heusler, Lucas S. |
| author_facet | Heusler, Lucas S. |
| author_role | aut |
| author_sort | Heusler, Lucas S. |
| author_variant | l s h ls lsh |
| building | Verbundindex |
| bvnumber | BV009015962 |
| classification_rvk | ZN 4960 |
| classification_tum | ELT 364d ELT 456d |
| ctrlnum | (OCoLC)70261152 (DE-599)BVBBV009015962 |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Microfilm Book |
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| genre_facet | Hochschulschrift |
| id | DE-604.BV009015962 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:28:37Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-005961487 |
| oclc_num | 70261152 |
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| owner | DE-29T DE-91 DE-BY-TUM DE-11 |
| owner_facet | DE-29T DE-91 DE-BY-TUM DE-11 |
| physical | 2 Mikrofiches 24x |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
| record_format | marc |
| spelling | Heusler, Lucas S. Verfasser aut Transistor sizing for timing optimization of combinational digital CMOS circuits by Lucas Sebastian Heusler 1990 2 Mikrofiches 24x txt rdacontent h rdamedia he rdacarrier Zürich, Techn. Hochsch., Diss.. - Mikroreprod. e. Ms. IX, 102 S. Datenverarbeitung Metal oxide semiconductors, Complementary Timing circuits Data processing Transistor circuits Data processing Schaltnetz (DE-588)4052053-5 gnd rswk-swf CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf Nichtlineare Optimierung (DE-588)4128192-5 gnd rswk-swf CMOS (DE-588)4010319-5 gnd rswk-swf Bemessung (DE-588)4005461-5 gnd rswk-swf Transistor (DE-588)4060646-6 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Schaltnetz (DE-588)4052053-5 s CMOS (DE-588)4010319-5 s Transistor (DE-588)4060646-6 s Nichtlineare Optimierung (DE-588)4128192-5 s DE-604 CMOS-Schaltung (DE-588)4148111-2 s Bemessung (DE-588)4005461-5 s 1\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Heusler, Lucas S. Transistor sizing for timing optimization of combinational digital CMOS circuits Datenverarbeitung Metal oxide semiconductors, Complementary Timing circuits Data processing Transistor circuits Data processing Schaltnetz (DE-588)4052053-5 gnd CMOS-Schaltung (DE-588)4148111-2 gnd Nichtlineare Optimierung (DE-588)4128192-5 gnd CMOS (DE-588)4010319-5 gnd Bemessung (DE-588)4005461-5 gnd Transistor (DE-588)4060646-6 gnd |
| subject_GND | (DE-588)4052053-5 (DE-588)4148111-2 (DE-588)4128192-5 (DE-588)4010319-5 (DE-588)4005461-5 (DE-588)4060646-6 (DE-588)4113937-9 |
| title | Transistor sizing for timing optimization of combinational digital CMOS circuits |
| title_auth | Transistor sizing for timing optimization of combinational digital CMOS circuits |
| title_exact_search | Transistor sizing for timing optimization of combinational digital CMOS circuits |
| title_full | Transistor sizing for timing optimization of combinational digital CMOS circuits by Lucas Sebastian Heusler |
| title_fullStr | Transistor sizing for timing optimization of combinational digital CMOS circuits by Lucas Sebastian Heusler |
| title_full_unstemmed | Transistor sizing for timing optimization of combinational digital CMOS circuits by Lucas Sebastian Heusler |
| title_short | Transistor sizing for timing optimization of combinational digital CMOS circuits |
| title_sort | transistor sizing for timing optimization of combinational digital cmos circuits |
| topic | Datenverarbeitung Metal oxide semiconductors, Complementary Timing circuits Data processing Transistor circuits Data processing Schaltnetz (DE-588)4052053-5 gnd CMOS-Schaltung (DE-588)4148111-2 gnd Nichtlineare Optimierung (DE-588)4128192-5 gnd CMOS (DE-588)4010319-5 gnd Bemessung (DE-588)4005461-5 gnd Transistor (DE-588)4060646-6 gnd |
| topic_facet | Datenverarbeitung Metal oxide semiconductors, Complementary Timing circuits Data processing Transistor circuits Data processing Schaltnetz CMOS-Schaltung Nichtlineare Optimierung CMOS Bemessung Transistor Hochschulschrift |
| work_keys_str_mv | AT heuslerlucass transistorsizingfortimingoptimizationofcombinationaldigitalcmoscircuits |