Reduction of network cost and wiring in Ranade's butterfly routing:

Abstract: "The class of n-input butterfly networks is very important for the design of scalable parallel machines because of constant node degree, depth log n and the existence of routing algorithms capable of delivering n log n packets, forming a log n-relation (log n packets destined to each...

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Bibliographic Details
Main Authors: Cross, David (Author), Drefenstedt, Reinhard (Author), Keller, Jörg (Author)
Format: Book
Language:English
Published: Amsterdam 1992
Series:Centrum voor Wiskunde en Informatica <Amsterdam> / Department of Computer Science: Report CS 92,43
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Summary:Abstract: "The class of n-input butterfly networks is very important for the design of scalable parallel machines because of constant node degree, depth log n and the existence of routing algorithms capable of delivering n log n packets, forming a log n-relation (log n packets destined to each output), in time O(log n) with constant length buffers. Implementations however who ugly wiring. We present a method that, in comparison to the obvious implementation, reduces the number of chips and the number of links between chips in Ranade's butterfly routing by a factor of more than two. The chips remain connected as a butterfly network. This reduction in space simplifies cooling, power supply and allows for shorter links thus reducing wire delay."
Physical Description:6 S.

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