Design of a Bit-sliced network for a shared-memory multiprocessor system:
Abstract: "Packet switching crossbar switches with matching data widths and addressing range will provide the most efficient building blocks for a shared memory multi-processor network, providing the lowest latency consistent with high data throughput and error tolerance for a low device count....
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Edinburgh
1992
|
| Schriftenreihe: | University <Edinburgh> / Department of Computer Science: CSR
19 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "Packet switching crossbar switches with matching data widths and addressing range will provide the most efficient building blocks for a shared memory multi-processor network, providing the lowest latency consistent with high data throughput and error tolerance for a low device count. A demonstration device for a 4*4 crossbar switch with 2-bit data paths has been implemented. Results from this show that the pad-bound assumption, inherent in the original argument would be true for a full custom implementation in a sub-micron process. Simulation for the arbitration method used is given, predicting that fairness is only slightly compromised against optimal for the sake of considerable reduction in complexity, if priority is based solely on queue length." |
| Beschreibung: | 23 S. |
Internformat
MARC
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| 005 | 19940721 | ||
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| 035 | |a (DE-599)BVBBV008993636 | ||
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| 041 | 0 | |a eng | |
| 049 | |a DE-29T |a DE-91G | ||
| 100 | 1 | |a Rogers, D. J. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Design of a Bit-sliced network for a shared-memory multiprocessor system |c D. J. Rogers & R. N. Ibbett |
| 264 | 1 | |a Edinburgh |c 1992 | |
| 300 | |a 23 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a University <Edinburgh> / Department of Computer Science: CSR |v 19 | |
| 520 | 3 | |a Abstract: "Packet switching crossbar switches with matching data widths and addressing range will provide the most efficient building blocks for a shared memory multi-processor network, providing the lowest latency consistent with high data throughput and error tolerance for a low device count. A demonstration device for a 4*4 crossbar switch with 2-bit data paths has been implemented. Results from this show that the pad-bound assumption, inherent in the original argument would be true for a full custom implementation in a sub-micron process. Simulation for the arbitration method used is given, predicting that fairness is only slightly compromised against optimal for the sake of considerable reduction in complexity, if priority is based solely on queue length." | |
| 650 | 7 | |a Computer hardware |2 sigle | |
| 650 | 7 | |a Computer software |2 sigle | |
| 650 | 4 | |a Multiprocessors | |
| 700 | 1 | |a Ibbett, R. N. |e Verfasser |4 aut | |
| 810 | 2 | |a Department of Computer Science: CSR |t University <Edinburgh> |v 19 |w (DE-604)BV008906637 |9 19 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-005942373 | ||
Datensatz im Suchindex
| _version_ | 1804123336209334272 |
|---|---|
| any_adam_object | |
| author | Rogers, D. J. Ibbett, R. N. |
| author_facet | Rogers, D. J. Ibbett, R. N. |
| author_role | aut aut |
| author_sort | Rogers, D. J. |
| author_variant | d j r dj djr r n i rn rni |
| building | Verbundindex |
| bvnumber | BV008993636 |
| ctrlnum | (OCoLC)32408785 (DE-599)BVBBV008993636 |
| format | Book |
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| id | DE-604.BV008993636 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:28:09Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-005942373 |
| oclc_num | 32408785 |
| open_access_boolean | |
| owner | DE-29T DE-91G DE-BY-TUM |
| owner_facet | DE-29T DE-91G DE-BY-TUM |
| physical | 23 S. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| record_format | marc |
| series2 | University <Edinburgh> / Department of Computer Science: CSR |
| spelling | Rogers, D. J. Verfasser aut Design of a Bit-sliced network for a shared-memory multiprocessor system D. J. Rogers & R. N. Ibbett Edinburgh 1992 23 S. txt rdacontent n rdamedia nc rdacarrier University <Edinburgh> / Department of Computer Science: CSR 19 Abstract: "Packet switching crossbar switches with matching data widths and addressing range will provide the most efficient building blocks for a shared memory multi-processor network, providing the lowest latency consistent with high data throughput and error tolerance for a low device count. A demonstration device for a 4*4 crossbar switch with 2-bit data paths has been implemented. Results from this show that the pad-bound assumption, inherent in the original argument would be true for a full custom implementation in a sub-micron process. Simulation for the arbitration method used is given, predicting that fairness is only slightly compromised against optimal for the sake of considerable reduction in complexity, if priority is based solely on queue length." Computer hardware sigle Computer software sigle Multiprocessors Ibbett, R. N. Verfasser aut Department of Computer Science: CSR University <Edinburgh> 19 (DE-604)BV008906637 19 |
| spellingShingle | Rogers, D. J. Ibbett, R. N. Design of a Bit-sliced network for a shared-memory multiprocessor system Computer hardware sigle Computer software sigle Multiprocessors |
| title | Design of a Bit-sliced network for a shared-memory multiprocessor system |
| title_auth | Design of a Bit-sliced network for a shared-memory multiprocessor system |
| title_exact_search | Design of a Bit-sliced network for a shared-memory multiprocessor system |
| title_full | Design of a Bit-sliced network for a shared-memory multiprocessor system D. J. Rogers & R. N. Ibbett |
| title_fullStr | Design of a Bit-sliced network for a shared-memory multiprocessor system D. J. Rogers & R. N. Ibbett |
| title_full_unstemmed | Design of a Bit-sliced network for a shared-memory multiprocessor system D. J. Rogers & R. N. Ibbett |
| title_short | Design of a Bit-sliced network for a shared-memory multiprocessor system |
| title_sort | design of a bit sliced network for a shared memory multiprocessor system |
| topic | Computer hardware sigle Computer software sigle Multiprocessors |
| topic_facet | Computer hardware Computer software Multiprocessors |
| volume_link | (DE-604)BV008906637 |
| work_keys_str_mv | AT rogersdj designofabitslicednetworkforasharedmemorymultiprocessorsystem AT ibbettrn designofabitslicednetworkforasharedmemorymultiprocessorsystem |