Soft configurable wafer scale integration: design, implementation and yield analysis
Abstract: "Soft-Configurable Wafer Scale Integration uses software controlled switches to connect up the fault-free parts of a wafer. Compared to hard configuration, the soft configurable approach has the advantages of providing low-cost connections and runtime fault tolerance. The dissertation...
Saved in:
| Main Author: | |
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| Format: | Book |
| Language: | English |
| Published: |
Stanford, Calif.
1990
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| Series: | Stanford University / Computer Science Department: Report STAN CS
1334 |
| Subjects: | |
| Summary: | Abstract: "Soft-Configurable Wafer Scale Integration uses software controlled switches to connect up the fault-free parts of a wafer. Compared to hard configuration, the soft configurable approach has the advantages of providing low-cost connections and runtime fault tolerance. The dissertation describes how to achieve soft configuration with high performance, presenting a pipelined memory system implemented using this approach. The yield of the prototype is evaluated in two phases. Fault simulation applies measured defect statistics to the layout to predict the yield of each circuit unit. These unit yields are combined to produce wafer yields using redundancy models appropriate to wafer scale integration The redundancy models constrain wafer yield by system requirements such as the minimum number of working circuit units, and whether these working units are distributed evenly around the wafer. Choice of redundancy model significantly affects the resulting wafer yield. |
| Item Description: | Zugl.: Stanford, Calif., Univ., Diss. |
| Physical Description: | VII, 116 S. |
Staff View
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| 500 | |a Zugl.: Stanford, Calif., Univ., Diss. | ||
| 520 | 3 | |a Abstract: "Soft-Configurable Wafer Scale Integration uses software controlled switches to connect up the fault-free parts of a wafer. Compared to hard configuration, the soft configurable approach has the advantages of providing low-cost connections and runtime fault tolerance. The dissertation describes how to achieve soft configuration with high performance, presenting a pipelined memory system implemented using this approach. The yield of the prototype is evaluated in two phases. Fault simulation applies measured defect statistics to the layout to predict the yield of each circuit unit. These unit yields are combined to produce wafer yields using redundancy models appropriate to wafer scale integration | |
| 520 | 3 | |a The redundancy models constrain wafer yield by system requirements such as the minimum number of working circuit units, and whether these working units are distributed evenly around the wafer. Choice of redundancy model significantly affects the resulting wafer yield. | |
| 650 | 4 | |a Fault-tolerant computing | |
| 650 | 4 | |a Integrated circuits |x Wafer-scale integration | |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 810 | 2 | |a Computer Science Department: Report STAN CS |t Stanford University |v 1334 |w (DE-604)BV008928280 |9 1334 | |
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| indexdate | 2024-07-09T17:27:46Z |
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| language | English |
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| physical | VII, 116 S. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
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| series2 | Stanford University / Computer Science Department: Report STAN CS |
| spelling | Blatt, Miriam G. Verfasser aut Soft configurable wafer scale integration design, implementation and yield analysis by Miriam Greta Blatt Stanford, Calif. 1990 VII, 116 S. txt rdacontent n rdamedia nc rdacarrier Stanford University / Computer Science Department: Report STAN CS 1334 Zugl.: Stanford, Calif., Univ., Diss. Abstract: "Soft-Configurable Wafer Scale Integration uses software controlled switches to connect up the fault-free parts of a wafer. Compared to hard configuration, the soft configurable approach has the advantages of providing low-cost connections and runtime fault tolerance. The dissertation describes how to achieve soft configuration with high performance, presenting a pipelined memory system implemented using this approach. The yield of the prototype is evaluated in two phases. Fault simulation applies measured defect statistics to the layout to predict the yield of each circuit unit. These unit yields are combined to produce wafer yields using redundancy models appropriate to wafer scale integration The redundancy models constrain wafer yield by system requirements such as the minimum number of working circuit units, and whether these working units are distributed evenly around the wafer. Choice of redundancy model significantly affects the resulting wafer yield. Fault-tolerant computing Integrated circuits Wafer-scale integration (DE-588)4113937-9 Hochschulschrift gnd-content Computer Science Department: Report STAN CS Stanford University 1334 (DE-604)BV008928280 1334 |
| spellingShingle | Blatt, Miriam G. Soft configurable wafer scale integration design, implementation and yield analysis Fault-tolerant computing Integrated circuits Wafer-scale integration |
| subject_GND | (DE-588)4113937-9 |
| title | Soft configurable wafer scale integration design, implementation and yield analysis |
| title_auth | Soft configurable wafer scale integration design, implementation and yield analysis |
| title_exact_search | Soft configurable wafer scale integration design, implementation and yield analysis |
| title_full | Soft configurable wafer scale integration design, implementation and yield analysis by Miriam Greta Blatt |
| title_fullStr | Soft configurable wafer scale integration design, implementation and yield analysis by Miriam Greta Blatt |
| title_full_unstemmed | Soft configurable wafer scale integration design, implementation and yield analysis by Miriam Greta Blatt |
| title_short | Soft configurable wafer scale integration |
| title_sort | soft configurable wafer scale integration design implementation and yield analysis |
| title_sub | design, implementation and yield analysis |
| topic | Fault-tolerant computing Integrated circuits Wafer-scale integration |
| topic_facet | Fault-tolerant computing Integrated circuits Wafer-scale integration Hochschulschrift |
| volume_link | (DE-604)BV008928280 |
| work_keys_str_mv | AT blattmiriamg softconfigurablewaferscaleintegrationdesignimplementationandyieldanalysis |